CY22050 Cypress Semiconductor, CY22050 Datasheet - Page 2

• Manufacturer Part Number: CY22050
• Description: One-PLL General Purpose Flash Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07006 Rev. *D
CY22050 Pin Summary
Functional Description
The CY22050 is the next-generation programmable FTG
(frequency timing generator) for use in networking, telecom-
munication, datacom, and other general-purpose applications.
The CY22050 offers up to six configurable outputs in a 16-pin
TSSOP, running off a 3.3V power supply. The on-chip
reference oscillator is designed to run off an 8–30-MHz crystal,
or a 1–133-MHz external clock signal.
The CY22050 has a single PLL driving 6 programmable output
clocks. The output clocks are derived from the PLL or the
reference frequency (REF). Output post dividers are available
for either. Four of the outputs can be set as 3.3V or 2.5V, for
use in a wide variety of portable and low-power applications.
Field Programming the CY22050F
The CY22050 is programmed at the package level, i.e., in a
programmer socket. The CY22050 is flash-technology based,
so the parts can be reprogrammed up to 100 times. This allows
for fast and easy design changes and product updates, and
eliminates any issues with old and out-of-date inventory.
Samples and small prototype quantities can be programmed
on the CY3672 programmer. Cypress’s value-added distri-
bution partners and third-party programming systems from BP
Microsystems, HiLo Systems, and others are available for
large-production quantities.
CyClocksRT Software
CyClocksRT™ is an easy-to-use software application that
allows the user to custom-configure the CY22050. Users can
specify the REF, PLL frequency, output frequencies and/or
post-dividers, and different functional options. CyClocksRT
Notes:
1. The CY22050 has no internal pull-up or pull-down resistors. PWRDWN and OE pins need to be driven as appropriate or tied to power or ground.
2. Float XOUT if XIN is driven by an external clock source.
PWRDWN
XOUT
LCLK1
LCLK2
LCLK3
LCLK4
Name
AVDD
VDDL
AVSS
VSSL
CLK5
CLK6
OE
VDD
VSS
XIN
[1]
[2]
[1]
Pin Number
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
Reference Input. Driven by a crystal (8 MHz–30 MHz) or external clock (1 MHz–133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal, based
on manufacturer, process, performance, or quality.
3.3V voltage supply
3.3V analog voltage supply
Power Down. When pin 4 is driven LOW, the CY22050 will go into shut-down mode.
Analog ground
LCLK ground
Configurable clock output 1 at V
Configurable clock output 2 at V
Configurable clock output 3 at V
Output Enable. When pin 10 is driven LOW, all outputs are three-stated.
LCLK voltage supply (2.5V or 3.3V)
Configurable clock output 4 at V
Ground
Configurable clock output 5 (3.3V)
Configurable clock output 6 (3.3V)
Reference output
DDL
DDL
DDL
DDL
outputs
programming the CY22050.
CyClocksRT can be downloaded free of charge from the
Cypress website at http://www.cypress.com.
CY3672 FTG Development Kit
The Cypress CY3672 FTG Development Kit comes complete
with everything needed to design with the CY22050 and
program samples and small prototype quantities. The kit
comes with the latest version of CyClocksRT and a small
portable programmer that connects to a PC serial port for
on-the-fly programming of custom frequencies.
The JEDEC file output of CyClocksRT can be downloaded to
the portable programmer for small-volume programming, or
for use with a production programming system for larger
volumes.
Applications
Controlling Jitter
Jitter is defined in many ways, including: phase noise,
long-term jitter, cycle-to-cycle jitter, period jitter, absolute jitter,
and deterministic jitter. These jitter terms are usually given in
terms of rms, peak-to-peak, or in the case of phase noise
dBC/Hz with respect to the fundamental frequency. Actual
jitter is dependent on XIN jitter and edge rate, number of active
outputs, output frequencies, V
and output load.
Power supply noise and clock output loading are two major
system sources of clock jitter. Power supply noise can be
mitigated by proper power supply decoupling (0.1-µF ceramic
cap) of the clock and ensuring a low-impedance ground to the
level (3.3V or 2.5V)
level (3.3V or 2.5V)
level (3.3V or 2.5V)
level (3.3V or 2.5V)
Description
an
industry-standard
DDL
(2.5V or 3.3V), temperature,
JEDEC
CY22050
file
Page 2 of 9
used
for