CY2305 Cypress Semiconductor, CY2305 Datasheet - Page 2

• Manufacturer Part Number: CY2305
• Description: CY2305 and CY2309 as PCI and SDRAM Buffers
• Manufacturer: Cypress Semiconductor

Lead or Lag Adjustments
To adjust the lead or lag of the outputs on the CY2305 or
CY2309, one must understand the relationships between
REF and CLKOUT, and the relationship between CLKOUT
and the other outputs. To understand the relationship, first we
need to understand a few properties of the CY2305 and
CY2309 Phase Locked Loops. The PLL senses the phase of
the CLKOUT pin at a threshold of V
the REF pin at the same V
their transition at the same time (including CLKOUT). Chang-
ing the load on an output changes its rise time and therefore
how long it takes the output to get to the V
Using these properties to our advantage, we can then adjust
the time when the outputs reach the V
to when the REF input reaches the V
OUT output however cannot be adjusted: it will always have
dd
/2 threshold. All the outputs start
dd
dd
/2 threshold. The CLK-
/2 and compares it to
dd
/2 threshold relative
dd
/2 threshold.
Figure 3. Lead Lag Adjustments
2
CY2305 and CY2309 as PCI and SDRAM Buffers
zero delay from the REF input at V
advanced by loading the CLKOUT output more heavily than
the other outputs or can be delayed by loading CLKOUT more
lightly than the other outputs. Figure 3 shows how many ps
the outputs are moved vs. the difference in the loading be-
tween CLKOUT and the other outputs. As a rough guideline,
the adjustment is 50 ps/pF of loading difference. Note: the
zero delay buffer will always adjust itself to keep the V
point of the output at zero delay from the V
reference. If the application requires the outputs of the zero
delay buffer to have zero delay from another output of the
reference clock chip, the output of the clock chip that is driving
the zero delay buffer must be loaded the same as the other
outputs of the clock chip or the outputs of the zero delay buffer
will be advanced/delayed with reference to those other out-
puts.
dd
/2. The outputs can be
dd
/2 point of the
dd
/2