CY28409 Cypress Semiconductor, CY28409 Datasheet - Page 5

• Manufacturer Part Number: CY28409
• Description: Clock Synthesizer with Differential SRC and CPU Outputs
• Manufacturer: Cypress Semiconductor

Document #: 38-07445 Rev. *B
Byte 0:Control Register 0 (continued)
Byte 1: Control Register 1
Byte 2: Control Register 2
Byte 3: Control Register 3
Bit
Bit
Bit
Bit
5
4
3
7
6
2
1
0
7
6
3
2
1
0
7
6
5
4
3
2
1
0
Externally
Externally
Externally
Externally
Selected
Selected
Selected
Selected
@Pup
@Pup
@Pup
@Pup
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
SRCT, SRCC
SRCT, SRCC
Reserved
Reserved
Reserved
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
SRCT, SRCC
SRCT, SRCC
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
CPUT2, CPUC2
CPUT1, CPUC1
CPUT0, CPUC0
SW PCI STOP
PCI6
PCI_STP#
CPU_STP#
FS_B
FS_A
Name
Name
Name
Name
Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
Reserved, Set = 1
Reserved, Set = 1
Reserved, Set = 1
CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
CPUT/C1 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
CPUT/C0 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
SRCT/C Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
SRCT/C Stop Drive Mode
0 = Driven during PCI_STP, 1 = Three-state during PCI_STP
CPUT/C2 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C1 Pwrdwn Drive Mode
0 = Driven during power ‘down, 1 = Three-state during power-down
CPUT/C0 Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
CPUT/C2 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
CPUT/C1 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
CPUT/C0 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped
SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
PCI6 Output Enable
0 = Disabled, 1 = Enabled
PCI_STP# reflects the current value of the external PCI_STP# pin.
0 =PCI_STP# pin is low.
CPU_STP# reflects the current value of the external CPU_STP# pin.
0 = CPU_STP# pin is low.
FS_B reflects the value of the FS_B pin sampled on power-up.
FS_A reflects the value of the FS_A pin sampled on power-up.
Description
Description
Description
Description
CY28409
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