CY28409 Cypress Semiconductor, CY28409 Datasheet - Page 8

• Manufacturer Part Number: CY28409
• Description: Clock Synthesizer with Differential SRC and CPU Outputs
• Manufacturer: Cypress Semiconductor

Document #: 38-07445 Rev. *B
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
C s 1
Figure 1. Crystal Capacitive Clarification
Figure 2. Crystal Loading Example
C e 1
X 1
C i1
C lo c k C h ip
( C Y 2 8 4 0 9 )
X T A L
C i2
X 2
C e 2
C s 2
3 t o 6 p
3 3 p F
P in
T r im
T r a c e
2 . 8 p F
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
PD# (Power-down) Clarification
The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so as not to cause glitches
while changing to the low ‘stopped’ state.
PD# Assertion
When PD# is sampled low by two consecutive rising edges of
the CPUC clock then all clock outputs (except CPU) clocks
must be held low on their next high to low transition. CPU
clocks must be held with CPU clock pin driven high with a
value of 2 x Iref and CPUC undriven. Due to the state of
internal logic, stopping and holding the REF clock outputs in
the LOW state may require more than one clock cycle to
complete
CLe
Total Capacitance (as seen by the crystal)
=
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
Ce = 2 * CL – (Cs + Ci)
1
+
1
Ce2 + Cs2 + Ci2
1
CY28409
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