CY28419 Cypress Semiconductor, CY28419 Datasheet
CY28419
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CY28419 Summary of contents
Page 1
... PCI(0:6) VDD_PCI VSS_PCI PCI4 3V66_4/VCH PCI5 PCI6 PD# VDD_48MHz DOT_48 3V66_0 USB_48 3V66_1 VDD_3V66 VSS_3V66 3V66_2 3V66_3 SCLK • 3901 North First Street • CY28419 CPU Outputs SRC 3V66 PCI REF [ FS_B 2 55 VDD_A 3 54 VSS_A 4 53 ...
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... Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. 3.3V power supply for outputs. Ground for outputs. CY28419 Pin Description Page ...
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... The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 3. Command Code Definition Bit 7 (6:0) Bit 1 2 11:18 CY28419 has been sampled low, REF0 REF1 14.3 MHz 14.31 MHz REF/N REF/N 14.3 MHz 14.31 MHz 14 ...
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... Acknowledge from slave 20 Repeat start 21:27 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Acknowledge from master 39 Stop CY28419 Page ...
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... SRCT/C Stop drive mode 0 = Driven in PCI_STP Three-state in power-down CPUT/C2 Pwrdwn drive mode 0 = Driven in power-down Three-state in power-down CPUT/C1 Pwrdwn drive mode 0 = Driven in power-down Three-state in power-down CPUT/C0 Pwrdwn drive mode 0 = Driven in power-down Three-state in power-down Reserved Reserved Reserved CY28419 Description Description Description Page ...
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... Enabled VCH Select 66 MHz/48 MHz 0 = 3V66 mode VCH (48MHz) mode 3V66_4/VCH Output Enable 0 = Disabled Enabled 3V66_3 Output Enable 0 = Disabled Enabled 3V66_2 Output Enable 0 = Disabled Enabled 3V66_1 Output Enable 0 = Disabled Enabled 3V66_0 Output Enable 0 = Disabled Enabled CY28419 Description Description Description Page ...
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... Crystal Recommendations The CY28419 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28419 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... REF clock outputs in the LOW Pin state may require more than one clock cycle to complete. Cs2 Trace 2.8pF Ce2 Trim 33pF – (Cs + Ci) Total Capacitance (as seen by the crystal Ce2 + Cs2 + Ci2 Ce1 + Cs1 + Ci1 CY28419 ) Page ...
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... CPUT/C outputs must be driven to greater than 200 mV is less than 300 us. PD# CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz 3V66, 66MHz USB, 48MHz PCI, 33MHz REF Figure 4. Power-down Deassertion Timing Waveforms Document #: 38-07444 Rev. *D Tstable <1.8ms Tdrive_PWRDN# <300µS, >200mV CY28419 Page ...
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... Wait for Sample Sels Delay VTT_PWRGD# State 1 State 2 On Figure 5. VTTPWRGD Timing Diagram S1 VTT_PWRGD# = Low Delay >0.25mS S3 VDD_A = off Normal Operation VTT_PWRGD# = toggle CY28419 Device is not affected, VTT_PWRGD# is ignored State Sample Inputs straps Wait for <1.8ms Enable Outputs Page ...
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... The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source 69.841 Measured between 0.3V and 0. average over 1-µs duration Over 150 ms CY28419 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V – ...
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... Measured at crossing point V Measured at crossing point V = 0.175 Determined as a fraction of 2*(T Math average, see Figure 7 Math average, see Figure 7 See Figure 7. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.0V Measurement at 0.8V Measured between 0.8V and 2.0V Measurement at 1.5V CY28419 Min. Max 9.9970 10.003 OX 7.4978 7.5023 OX 5.9982 6.0018 OX 4 ...
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... Table 9. Maximum Lumped Capacitive Output Loads Offset Min. Max. PCI Clocks 1.5 ns 3.5 ns 3V66 Clocks USB Clock DOT Clock Value Tolerance REF Clock 0.0ns 1000 ps 0.0ns 1000 ps 0.0ns 1000 ps CY28419 Min. Max. 45 29.9910 30.0009 29.9910 30.1598 12.0 12.0 0.5 – – 45 20.8257 20.8340 8.994 10.486 8.794 10 ...
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... Reference R, Iref – V (3*Rr 475 1 2.32 mA REF REF Package Type CY28419 Output Current Voh @ Z Ioh = 6*Iref 0. Product Flow Commercial, 0 ° ° C Commercial, 0 ° ° C Commercial, 0 ° ° C ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 56-Lead Shrunk Small Outline Package O56 2 C system, provided that the system conforms to the I CY28419 51-85062-*C 51-85060-* Standard Specification ...
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... Document History Page Document Title: CY28419 Clock Synthesizer with Differential SRC and CPU Outputs Document Number: 38-07444 REV. ECN NO. Issue Date ** 121413 12/05/02 *A 127740 07/01/03 *B 128452 07/30/03 *C 129785 10/03/03 *D 203832 See ECN Document #: 38-07444 Rev. *D Orig. of Change RGL New Data Sheet RGL Added power-up requirements in the absolute maximum conditions table ...