CY28419 Cypress Semiconductor, CY28419 Datasheet - Page 14

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CY28419

Manufacturer Part Number
CY28419
Description
Clock Synthesizer
Manufacturer
Cypress Semiconductor
Datasheet

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Document #: 38-07444 Rev. *D
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
Table 10. CPU Clock Current Select Function
Ordering Information
CY28419OC
CY28419OCT
CY28419ZC
CY28419ZCT
Board Target Trace/Term Z
Part Number
Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
50 Ohms
2 .0 V
1 .5 V
0 .8 V
IR E F
C P U C
C P U T
4 7 5 Ω
T r
56-pin Shrunk Small Outline package (SSOP)
56-pin Shrunk Small Outline package (SSOP) – Tape and Reel
56-pin Thin Shrunk Small Outline package (TSSOP)
56-pin Thin Shrunk Small Outline package (TSSOP) – Tape and Reel Commercial, 0 ° to 70 ° C
-
3 3 Ω
3 3 Ω
3 .3 V
3 .3 V s ig n a ls
4 9 .9 Ω
4 9 .9 Ω
Figure 7. 0.7V Load Configuration
R
Reference R, Iref – V
tD C
REF
T
T
T f
P C B
P C B
= 475 1%, I
Package Type
0 V
REF
= 2.32 mA
DD
2 p F
2 p F
-
(3*Rr)
O u tp u t u n d e r T e s t
M e a s u r e m e n t
M e a s u r e m e n t
P o in t
P o in t
P ro b e
Output Current
L o a d C a p
Ioh = 6*Iref
Commercial, 0 ° to 70 ° C
Commercial, 0 ° to 70 ° C
Commercial, 0 ° to 70 ° C
Product Flow
CY28419
Page 14 of 16
0.7V @ 50
Voh @ Z

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