CY28435 Cypress Semiconductor, CY28435 Datasheet - Page 14

• Manufacturer Part Number: CY28435
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07664 Rev. *B
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a low value and held prior to turning off the VCOs and
the crystal oscillator.
PD (Power-down) – Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held low on their next
HIGH-to-LOW transition and differential clocks must be held
high or tri-stated (depending on the state of the control register
drive mode bit) on the next diff clock# HIGH-to-LOW transition
within four clock periods. When the SMBus PD drive mode bit
corresponding to the differential (CPU, SRC, and DOT) clock
output of interest is programmed to ‘0’, the clock output are
held with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff
clock#” tri-state. If the control register PD drive mode bit corre-
sponding to the output of interest is programmed to “1”, then
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
PCI, 33 MHz
USB, 48MHz
DOT96C
DOT96T
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
REF
PCI, 33MHz
USB, 48MHz
PD
DOT96C
DOT96T
Figure 5. Power-down Deassertion Timing Waveform
REF
Figure 4. Power-down Assertion Timing Waveform
PD
PRELIMINARY
Tdrive_PWRDN#
<300µS, >200mV
Tstable
<1.8ms
both the “Diff clock” and the “Diff clock#” are tri-state. Note the
example below shows CPUT = 133 MHz and PD drive mode
= ‘1’ for all differential outputs. This diagram and description is
applicable to valid CPU frequencies 100, 133, 166, 200, 266,
333 and 400 MHz. In the event that PD mode is desired as the
initial power-on state, PD must be asserted high in less than
10 µs after asserting Vtt_PwrGd#.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 µs of PD deassertion to a voltage greater than 200
mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
CY28435
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