CY28435 Cypress Semiconductor, CY28435 Datasheet - Page 3

• Manufacturer Part Number: CY28435
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07664 Rev. *B
Pin Description
Frequency Select Pins (FS_[A:E])
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C,FS_D and
FS_E inputs prior to VTT_PWRGD# assertion (as seen by the
clock synthesizer). Upon VTT_PWRGD# being sampled LOW
by the clock chip (indicating processor VTT voltage is stable),
the clock chip samples the FS_A, FS_B, FS_C,FS_D and
FS_E input values. For all logic levels of FS_A, FS_B,
FS_C,FS_D and FS_E, VTT_PWRGD# employs a one-shot
functionality in that once a valid low on VTT_PWRGD# has
53
54
Pin No.
FS_5
(byte 16
bit 5)
No Spread Spectrum and Center spread spectrum on CPU PLL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
FS_E
HW only FSEL_3
FS_C/REF1
SRESET#/PCI0
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FS_D
(continued)
Name
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
FS_C
FSEL_2
Input Conditions
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
FS_B
FSEL_1
O, PU 3.3V LVTTL output for Watchdog reset/33-MHz clock output.
Type
Figure 1. CPU and SRC Frequency Select Tables
I/O,
PD
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
FS_A
FSEL_0
3.3V-tolerant input for CPU frequency selection/Reference clock.
Selects test mode if pulled to V
Refer to DC Electrical Specifications table for V
tions.
When configured as SRESET# output this output becomes open drain type with a
high (>100 kΩ) internal pull-up resistor.
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
133.3333333
166.6666667
266.6666667
333.3333333
266.6666667
400.6451613
100.952381
133.968254
200.952381
PRELIMINARY
133.33
166.67
266.67
333.33
100.95
133.97
166.98
200.95
266.67
333.97
400.65
133.33
166.67
266.67
333.33
100.95
133.97
(MHz)
Output Frequency
CPU
100
200
400
167
334
100
200
400
100
200
400
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
(MHz)
SRC
100
100
100
100
100
100
100
100
100
100
100
100
100
100
167
167
167
167
167
167
167
167
167
been sampled, all further VTT_PWRGD#, FS_A, FS_B,
FS_C,FS_D and FS_E transitions will be ignored, except in
test mode.
FS_C is a three level input, when sampled at a voltage greater
than 2.1V by VTTPWRGD#, the device will enter test mode as
selected by the voltage level on the FS_B input.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Constant
CPU PLL
Gear
120
120
120
120
120
120
120
120
120
120
(G)
30
40
60
60
80
30
40
60
60
80
30
40
60
60
80
30
40
60
60
80
30
40
60
60
80
30
40
s
IHFS_C
CPU M
divider
60
60
63
60
60
63
60
63
63
60
63
60
60
62
60
60
63
60
60
63
60
63
63
60
63
60
60
62
60
60
63
60
60
63
60
63
63
Description
when VTT_PWRGD# is asserted LOW.
DEFAULT
CPU N
200
200
175
200
200
175
200
212
211
167
211
200
167
207
200
200
175
200
200
175
200
212
211
167
211
200
167
207
200
200
175
200
200
175
200
212
211
allowable
range for
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
167 - 250
211 - 262
200 - 250
167 - 250
207 - 258
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
167 - 250
211 - 262
200 - 250
167 - 250
207 - 258
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
CPU N
ILFS_C
DAF
,V
Constants
SRC PLL
IMFS_C
Gear
30
30
30
30
30
30
30
30
30
30
30
30
30
30
40
40
40
40
40
40
40
40
40
40
40
40
40
40
60
60
60
60
60
60
60
60
60
,V
divider (not
changeable
by user)
SRC M
IHFS_C
CY28435
Page 3 of 23
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
specifica-