CY28RS400 Cypress Semiconductor, CY28RS400 Datasheet - Page 7

• Manufacturer Part Number: CY28RS400
• Description: Clock Generator for ATI RS400 Chipset
• Manufacturer: Cypress Semiconductor

Document #: 38-07637 Rev. *B
Byte 5: Control Register 5 (continued)
Byte 6: Control Register 6
Byte 7: Vendor ID
Bit
Bit
Bit
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
HW
HW
HW
HW
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
TEST_MODE
TEST_SEL
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
Reserved
Reserved
Reserved
409_410
Name
Name
FS_C
Name
FS_B
FS_A
REF
REF/N or Tri-state Select
1 = REF/N Clock, 0 = Tri-state
Test Clock Mode Entry Control
1 = REF/N or Tri-state mode, 0 = Normal operation
REF output drive strength.
0 = Low drive, 1 = High drive.
Reserved
409_410 reflects the value of the 409_410 pin sampled on power up. 0 =
409_410 was low during VTT_PWRGD# assertion
FS_C Reflects the value of the FS_C pin sampled on power up. 0 = FS_C
was low during VTT_PWRGD# assertion.
FS_B Reflects the value of the FS_B pin sampled on power up. 0 = FS_B
was low during VTT_PWRGD# assertion.
FS_A Reflects the value of the FS_A pin sampled on power up. 0 = FS_A
was low during VTT_PWRGD# assertion.
SRC[T/C]3 CLKREQ#1 control
1 = SRC[T/C]3 stoppable by CLKREQ#1 pin
0 = SRC[T/C]3 free running
SRC[T/C]2 CLKREQ#1 control
1 = SRC[T/C]2 stoppable by CLKREQ#1 pin
0 = SRC[T/C]2 free running
SRC[T/C]1 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
SRC[T/C]0 CLKREQ#1 control
1 = SRC[T/C]1 stoppable by CLKREQ#1 pin
0 = SRC[T/C]1 free running
Reserved
Reserved
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Description
Description
CY28RS400
Page 7 of 19