AN2269 Freescale Semiconductor / Motorola, AN2269 Datasheet - Page 11

• Manufacturer Part Number: AN2269
• Description: Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus
• Manufacturer: Freescale Semiconductor / Motorola

4.1 Host Memory Controller
UPM Offset
Cycle Type
offset + b
offset + d
offset + 0
offset + 1
offset + 2
offset + 3
offset + 4
offset + 5
offset + 6
offset + 7
offset + 8
offset + 9
offset + a
offset + c
offset + e
offset + f
To achieve these states, perform the following steps:
1. Configure the host memory controller to enable mapping of the HDI16 registers in memory.
2. Configure the host HDI16 registers, synchronize the host and HDI16 sides, and enable the HDI16
3. Configure the host IDMA registers and channel buffer descriptors.
4. Configure the host I/O ports to enable DMA request lines.
The MPC8260 memory controller maps each HDI16 host register to a specific memory location. Bank 6
within the memory controller handles these accesses since this bank is free within the current
MPC8260ADS memory controller set-up. The Base and Option Registers are programmed to map the
HDI16 registers to a base memory address of 0x30000000, select a port size of 16 bits, and enable bursts
to the HDI16.
UPM A is selected to issue the required HDI16 signals, so the RAM array for this UPM must be loaded.
Within the example code, the host-side HDI16 registers are accessed via a type definition (HPORT) that
simply overlays the memory-mapped host register locations. Table 2 defines the hexadecimal values
loaded into the UPM RAM Array to obtain the required HDI16 timing signals.
service request signals from the host side.
Freescale Semiconductor, Inc.
Single Read
0xFFFFFC00
0x0FFFFC00
0x3FFFFC01
0x0FFFF000
0x0FFFF000
0x0FFFF000
0x0FFFF004
0x0FFFF000
For More Information On This Product,
0
Go to: www.freescale.com
Burst Read
0x0FFFFC80
0x0FFFFC84
0x0FFFFC01
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0x0FFFF000
0x0FFFF000
0x0FFFF008
Table 2. UPM RAM Array Values
0x8
Single Write
0xFFFFFFFF
0xFFFFFFFF
0x8FFF2C00
0x0FFF3C00
0x3FFF3C01
0xFFFFFFFF
0x0FFF3000
0x0FFF3404
0x18
Burst Write
0xFFFFFC01
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0x0FFF348C
0x0FFF3880
0x0FFF3000
0x0FFF3000
0x0FFF3000
0x20
Host Device Configuration
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
Refresh
0x30
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFFFFFF
Exception
0x3C
11