AN2269 Freescale Semiconductor / Motorola, AN2269 Datasheet - Page 16

• Manufacturer Part Number: AN2269
• Description: Interconnecting MPC8260 and MSC8101 ADS Boards Using DMA Transfers Across a 60x Bus
• Manufacturer: Freescale Semiconductor / Motorola

Source Code Files, Software Flow, and Register Settings
16
Host MPC8260
Module
Channel Configuration Registers
Interrupt Status Register (ISR)
Rx DMA Channel BD and
Status Register (BCSR)
Interrupt and Associated
Configure and enable
Configure and enable
Memory-Map HDI16
Core-Side Registers
Board Control and
Configure ADS’s
VADS8260_MT.reg
hdi16.c
upminit.c
dma.c
Mpc8260.h
hdi16.h
hdi16masks.h
dma.h
dmatest.h
for_diab/sbc82xx.lk
for_diab/makefile
DMA Complete
Set Host Flag 4
1 and 2 Set?
Host Flags
Filename
Start
End
Yes
Table 5. Source Code Project Files (Continued)
Freescale Semiconductor, Inc.
VisionClick configuration file to initialize the SDRAM and BCSR memory banks on the MPC8260ADS.
Initializes the HDI16, initializes the core DSP, sets up the test transmit pattern and the received test
pattern destination address, and passes control to the DMA routine.
Contains functions to map the memory of the HDI16 host interface for the HDI16 MSC8101 device by
initializing UPM A.
Exercises the DMA functionality using memory-to-memory in Dual-Access mode.
Handles the MPC8260 register memory-mapping.
Includes common header files, defines the HDI16 memory map, and defines the card_initialize (UPM
set-up) function prototype.
Defines bit masks for the HDI16 host registers and a timeout count value for wait loops.
Defines the do_dma function prototype.
Defines the DMA buffer, MSC8101ADS, and I/O port-specific constants.
Diab data link editor command file.
Diab makefile. Paths require changing to accommodate the user’s environment.
No
Figure 5. HDI16 MSC8101 Software Flow
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Channel Configuration Registers
Tx DMA Channel BD and
Configure and enable
Clear Interrupt
Point to next
Rx Buffer
Description
Rx
DMA Complete
Channel?
Interrupt
Rx or Tx
End
Channel Configuration Registers
Rx DMA Channel BD and
Configure and enable
Clear Interrupt
Point to next
Tx Buffer
Tx