AN2311 Freescale Semiconductor / Motorola, AN2311 Datasheet - Page 2

• Manufacturer Part Number: AN2311
• Description: Bootstrapping the MSC8101 Device Through the HDI16 Port
• Manufacturer: Freescale Semiconductor / Motorola

Hardware Implementation
2
At power-on reset, several pins that determine the boot source and chip mode of operation are sampled.
Table 1 shows the pins that enable the MSC8101 for HDI16 operation in 16-bit dual data strobe mode.
The MSC8101 device has a highly configurable memory controller with a user-programmable machine
(UPM) interface, a general-purpose chip select machine (GPCM), and an SDRAM machine.
The UPM-controlled 60x-compatible system bus and HDI16 port are both programmable. You can
program the memory controller and UPM RAM to meet all the MSC8101 host port timing requirements.
The UPM offers very flexible memory control options with one quarter clock resolution. However,
depending upon the CPM:bus clock ratio, the relative phases of this one quarter of one clock granularity
may vary. Timing needs may change with different clock ratios. To ensure that the timing
recommendations developed here hold true at any clock speed or ratio, the analysis is performed using
the maximum bus clock of 100 MHz and using only the invariable one half of one clock boundaries (T1
and T3) to change signals. Therefore, the recommendations hold true for anything less than a 100 MHz
bus clock.
During a read access, the MSC8101 device latches data on the falling edge rather than on the usual rising
clock edge. The result is a sufficient timing margin to incorporate data buffer data delay with the same
timing settings still in effect. The DLT3 bit must be set in the corresponding UPM word to indicate the
data latch point on the falling clock, and MxMR[GPL4DIS] must be set to enable this mode. In a real
system scenario, as shown in Figure 2, buffering can be required, so the timings must be adjusted
accordingly. Furthermore, the read and write strobe deassertion times are readily met with the illustrated
UPM configuration, but this is difficult to achieve with a competitive memory access profile in the
alternative GPCM-controlled case.
RSTCONF
EE0
HPE/EE1
BTM[0–1]/EE[4:5]
HDDS
H8BIT
Figure 1. MSC8101 Host to HDI16 Hardware Interface
Pin
Freescale Semiconductor, Inc.
MSC8101 Host
For More Information On This Product,
Go to: www.freescale.com
A[27–30]
PDQM0
D[0–15]
PGPL2
Table 1. Slave Hardware Pin Configuration
IRQ4
IRQ5
CS6
Value
01
1
0
1
1
0
BTM=01 MSC8101 boots from HDI16
Dual data strobe mode enabled
16-Bit mode selected
HPE=1, Host port Enabled
c
s
s
s
Description
HCS1
HRD
HWR
HA[0–3]
HD[0–15]
HTRQ
HRRQ
MSC8101 Slave