CY2PP3115 Cypress Semiconductor, CY2PP3115 Datasheet - Page 4

• Manufacturer Part Number: CY2PP3115
• Description: Differential Fanout Buffer
• Manufacturer: Cypress Semiconductor

Document #: 38-07502 Rev.*A
ECL DC Electrical Specifications
AC Electrical Specifications
Control (FSEL(A,B,C),CLK_SEL, MR and FSELD) (ECL single-ended)
V
V
V
V
I
Clock input pair CLK0, CLK0#,CLK1,CLK1# (ECL differential signals)
V
V
I
ECL Outputs QA((0:1),#),QB((0:2),#),QC((0:3),#),QD((0:5),#)(ECL differential signals)
V
V
Supply current and VBB
I
V
Clock input pair CLK0, CLK0#,CLK1,CLK1#(PECL or ECL differential signals)
V
V
F
T
ECL/PECL Clock Outputs QA((0:1),#),QB((0:2),#),QC((0:3),#),QD((0:5),#) (differential)
Vo
VMCR
tsk
tsk
Notes:
10. Input have internal pullup / pulldown or biasing resistors which affect the input current.
11. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
12. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input
13. Equivalent to a termination of 50
14. I
15. AC characteristics apply for parallel output termination of 50
16. VPP (AC) is the minimum differential ECL/PECL input swing required to maintain AC characteristics including tpd and device-to-device skew.
17. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR(AC) range and
18. The CY2PP3115 is fully operation up to 1.5 GHz.
IN
IN
EE
Parameter
Parameter
CLK
PD
EE2.5
EE3.3
IL
IH
PP
CMR
OH
OL
BB
PP
CMR
(P-P)
(O)
(O)
swing lies within the VPP (DC) specification.
(V
the input swing lies within the VPP(AC) specification. Violation of VCMR(AC) or VPP(AC) impacts the device propagation delay, device and part-to-part skew.
CC
OL
Calculation: ICC = (number of differential output pairs used) x (I
–VTT)/Rload +I
–2.5 Negative Power Supply
–3.3 Negative Power Supply
Input Voltage, Low
Input Voltage, High
Input Current
Differential input voltage
Differential cross point voltage
Input Current
Output High Voltage
Output Low Voltage
V
Maximum Quiescent Supply Current
without output termination current
Output reference voltage
Differential input voltage
Differential cross point voltage
Input Frequency
Propagation Delay CLK0 or CLK1 to
QA(0:1),QB(0:2),QC(0:3),QD(0:5) pair
Differential output voltage
(peak-to-peak)
Common Voltage Range
Output-to-output skew
Output-to-output skew (different
frequency)
EE
= –3.3V ± 5%,V
EE
.
[10]
[10]
Description
Description
[18]
Ω
to VTT.
EE
= –2.5V ± 5%
[11]
[16]
[12]
[17]
[14]
PRELIMINARY
Ω
to VTT.
660 MHz 50% duty cycle Standard load Differ-
–2.5V ± 5%, V
–3.3V ± 5%, V
V
Differential operation
Differential operation
V
I
I
V
I
Differential operation
Differential operation
50% duty cycle Standard load
660 MHz 50% duty cycle Standard load Differ-
ential Operation. See Table 2
Differential PRBS
fo < 50 MHz
fo < 0.8 GHz
fo < 1.0 GHz
fo < 1.5 GHz
ential Operation
660 MHz 50% duty cycle Standard load Differ-
ential Operation
OH
OL
BB
IN
IN
EE
OH
= 200 uA
= –5 ma
= V
= V
= –30 mA
pin
+ I
OL
IL
IL
) + IEE or I
or V
or V
Condition
[13]
IN
IN
[13]
EE
EE
= V
= V
CC
= 0.0V
= 0.0V
Condition
IH
IH
= (number of differential output pairs used) x (V
V
–33.135
–2.375
–1.945
–1.165
–1.945
–1.945
–1.620
EE
Min.
–1.2
0.1
–
+1.2
FastEdge™ Series
V
EE
0.375
Min.
0.45
600
0.1
0.4
0.3
V
–2.625
–3.465
–1.625
–0.880
–1.220
–
–
CY2PP3115
+ 1.2
Max.
I150I
I150I
CC
–0.5
–0.7
–1.5
–1.3
180
1.3
–1.425
OH
Page 4 of 12
–VTT)/Rload +
Max.
1500 MHz
1200
1.3
50
60
0
Unit
mA
uA
uA
V
V
V
V
V
V
V
V
V
Unit
ps
ps
ps
ps
V
V
V