AN2405 Freescale Semiconductor / Motorola, AN2405 Datasheet - Page 4

• Manufacturer Part Number: AN2405
• Description: Supplemental Information for LCD Interfacing for the MC9328MX1 Application Processor Application Note
• Manufacturer: Freescale Semiconductor / Motorola

LCD Interface Clock Settings
Figure 2 shows that the LCD controller’s clock input is PERCLK2. PERCLK2, with respect to the LCDC, is
known as LCDC_CLK. Therefore, LCDC_CLK and HCLK are derived from the same clock source, the output of
the System PLL (System PLLCLK).
Please refer to the i.MX reference manual for PCLKDIV2 and BCLKDIV divider settings and programming.
4
HCLK and LCDC_CLK must follow the following relationship for the LCDC to
work properly:
LCDC_CLK = PERCLK2 = (System PLLCLK) / (PCLKDIV2)
HCLK = (System PLLCLK) / (BCLKDIV)
However, when BCLKDIV = 1 (for example BCLK_DIV setting = 0x0) then
HCLK = (System PLLCLK). In this case the divider PCLKDIV2 can be any value.
Also, when BCLK_DIV = 2 (for example BCLK_DIV setting = 0x1) then HCLK
= (System PLLCLK) / 2. In this case, the divider PCLK_DIV2 must be 3, 7, or 15
and so on.
This method ensures the rising clock edge of LCDC_CLK is synchronized with the
rising edge of HCLK, otherwise timing problems occur. Consequently, the output
of the LCDC is unpredictable.
i.MX Supplemental Information for LCD Interfacing Application Note, Rev. 1.1
Figure 2. i.MX Clock Controller Module
WARNING:
Freescale Semiconductor
LCDC_CLK
LCDC
To
as