AN2405 Freescale Semiconductor / Motorola, AN2405 Datasheet - Page 8

• Manufacturer Part Number: AN2405
• Description: Supplemental Information for LCD Interfacing for the MC9328MX1 Application Processor Application Note
• Manufacturer: Freescale Semiconductor / Motorola

Timing
4.2.2
Within the non-display period, the position of VSYNC relative to the HSYNC is the same in each HSYNC period.
This applies for both positive and negative going edge of VSYNC.
8
Ts is the LSCLK period which equals LCDC_CLK / (PCD + 1).
• VSYNC, HSYNC and LOE can be programmed as active high or active low. In the above timing diagram, all these 3
• The polarity of LSCLK and LD[15:0] can also be programmed.
• By default, LSCLK is idle when LOE is non-active.
• If register bit sclk_idle equals 1, LSCLK is active when LOE is non-active, excluding the HYSNC idle period and
• If register bit sclk_sel equals 1, LSCLK is always active.
• XMAX is defined in unit of pixel.
• Formula for period of VSYNC = T2 * YMAX + T1+T3+T4
Symbol
signals are active low.
dummy state, for example T5, T6, T7, and T8.
T8
LD[15:0]
L
L
HSYNC
VSYNC
LOE
TFT Timing for Non-Display Region
C
c
c
c
Dummy idle state (Sharp = 1)
LD[15:0]
HSYNC
VSYNC
LOE
i.MX Supplemental Information for LCD Interfacing Application Note, Rev. 1.1
Figure 6. TFT Panel Timing Waveform for Non-Display Region
Table 4. TFT Panel Timing for Display Region (continued)
Parameter
Allowed Register
Minimum Value
–
Actual Value
Freescale Semiconductor
3
Unit
Ts