AN2514 Freescale Semiconductor / Motorola, AN2514 Datasheet - Page 16
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AN2514
Manufacturer Part Number
AN2514
Description
3-Phase Sine Wave Generator TPU Function Set
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
1.AN2514.pdf
(28 pages)
AN2514/D
16
The MPW is written by the CPU. The MPW depends on the whole TPU unit
configuration, especially the lengths of the longest states of the other functions,
and their priorities, running on the same TPU. The MPW has to be correctly
calculated at the time the whole TPU unit is configured.
When 3Sin_top and 3Sin_bottom are running alone on one TPU, the minimum
pulse width can be calculated according to
case timing. The bottom channel low to high transition runs the HL state that
sets the following high to low transition. The HL state lasts 2 IMB clock cycles
(see
which takes 10 IMB clock cycles. So the time necessary to set the next
transition on the bottom channel is 12 IMB clock cycles. In addition, there is a
latency between the low to high transition and the start of the HL state. The top
channel state LH_C7, which is serviced at the time, causes the latency. The
3-Phase Sine Wave Generator TPU Function Set (3Sin)
Freescale Semiconductor, Inc.
Table
For More Information On This Product,
10). Each state is preceded by the Time Slot Transition (TST),
Go to: www.freescale.com
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Figure 6. Timing of the worst case
Figure 5. Effect of limitation
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6. This illustrates the worst
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