AN2676 Freescale Semiconductor / Motorola, AN2676 Datasheet - Page 3

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AN2676

Manufacturer Part Number
AN2676
Description
Image Capture with i.MX21
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
4 Initialization
4.1 Power Saving
The clock trees connected to the CSI, I
off by default in the Clock Control Module for power saving purpose. The clock must be enabled first.
4.2 IO Port
The pin assignments for the CSI, I
default. They must be enabled for functional pins first.
5 Sensor Interface
5.1 Traditional Timing
The traditional timing interface employs 3 clock signals and an 8-bit or 10-bit data bus.
Table 3 shows the clock signals.
MOTOROLA
Module
LCDC
DMA
PRP
CSI
I
2
C
Table 1. Clock Trees for the CSI, I2C, DMA, PRP, and LCDC Module
Horizontal Sync
Signal Name
Vertical Sync
Pixel Clock
Module
LCDC
Table 2. Pin Outs for CSI, I
CSI
I
2
Freescale Semiconductor, Inc.
C
For More Information On This Product,
Table 3. Traditional Timing Interface
2
C, and LCDC modules, shown in Table 2, are set to GPIO ports by
MC9328MX21 Application Note
Abbreviation
Peripheral Clock Control Register
2
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C, DMA, PRP, and LCDC module, shown in Table 1, are turned
HSYNC
PIXCLK
VSYNC
PCCR0
PCCR0
PCCR0
PCCR0
PCCR0
Start of frame (SOF)
Start of line and validate pixel clock
Carry pixel data
2
C, and LCDC Modules
Meaning
PD[18:17]
PB[21:10]
PA[31:5]
Port
Enable Bit
30, 23
27, 15
31
12
26
Initialization
3

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