AN2676 Freescale Semiconductor / Motorola, AN2676 Datasheet - Page 4

• Manufacturer Part Number: AN2676
• Description: Image Capture with i.MX21
• Manufacturer: Freescale Semiconductor / Motorola

Sensor Interface
The basic operation of traditional timing is Gated-Clock Mode as shown in Figure 2.
The start of frame (SOF) interrupt is generated upon the rising or falling edge of the VSYNC. HSYNC and
PIXCLK are internally AND-ed together to provide the valid pixel clock signal. The polarity of HSYNC
can be active-high or active-low. Data is latched to the FIFO on every valid pixel clock edge. Valid edges
can be either rising or falling.
Configuration of the timing details is through the CSI module Control Register 1 (CR1).
5.1.1 Clock Scheme
The CSI module is designed to accept input signals that are asynchronous to the system clock (HCLK).
Synchronization is done internally as long as the following relationship holds:
Sensors usually run on a single master clock (MCLK) and use it to divide out the pixel clock. MCLK can
be taken from the CSI module or other clock source.
5.1.2 DMA Synchronization Issue
When using DMA in non-repeat mode for the CSI module, synchronization is an important issue.
Consider the timing of VSYNC as shown in Figure 3 on page 4.
4
VSYNC
D[7..0]
HCLK
Freescale Semiconductor, Inc.
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Figure 2. Gated-Clock Mode Timing
SOF
MC9328MX21 Application Note
Figure 3. Timing of VSYNC
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Latency
≥ 2
×
PIXCLK
Valid Data
MOTOROLA
Eqn. 1