AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 10

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

MC9S12NE64 Integrated Ethernet Controller
These registers can be used to configure the internal bus clock to 25 MHz, which is required by the
MC9S12NE64 when operating at 100 Mbps. To configure the internal bus clock to 25 MHz with a 25-MHz
clock input, the PLL must be configured and initialized. This section discusses the initialization of the PLL.
The PLL can be configured as a frequency multiplier to run the MCU from a different timebase than that
of the incoming OSCCLK signal.
To select the timebase from which the system clock (SYSCLK) will be derived, the PLLSEL bit of the
CLKSEL register must be configured. SYSCLK can be either the OSCCLK signal coming from the OSC
module or the PLLCLK signal coming from the CRG PLL block. SYSCLK then becomes the source from
which both the core and the bus clocks are computed. Equation 1 and Equation 2 show the relationship
between the SYSCLK signal and the core and the bus clocks.
The PLLSEL bit configures the CRG clock PLL switch. If the PLLSEL bit is set, the system clocks are
derived from PLLCLK. If the PLLSEL bit is cleared, SYSCLK is derived from OSCCLK. So, depending on
the state of the PLLSEL bit, the bus clock can be calculated two different ways:
For MC9S12NE64, the PLLSEL bit must be set. Configuring the PLLCLK signal to the appropriate values
to achieve a 25-MHz SYSCLK signal requires configuring the CRG synthesizer register (SYNR) and CRG
reference divider register (REFDV). CRG registers include:
The SYNR and REFDV values together modify the incoming signal into the PLL block, OSCCLK. The
combined contribution of these registers to the value of PLLCLK is shown in Equation 4.
FLASH Clock
The oscillator clock is the input for the FLASH module. To perform FLASH program or erase operations,
the internal FLASH clock frequency (f
10
•
•
Equation 1:
Equation 2:
Equation 3: (In Equation 3, f
Equation
SYNR — 6-bit value that controls the multiplication factor of the PLL. If PLLSEL is asserted, the
OSCCLK signal is multiplied by 2 × (SYNR + 1).
REFDV — 4-bit value that provides a finer granularity for the PLL multiplier steps. If PLLSEL is
asserted, the OSCCLK signal is divided by (REFDV + 1).
if PLLSEL = 1, f
if PLLSEL = 0, f
4:
f
Core
Core
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
Core
f
Bus
f
PLL
PLL
= f
= f
= f
=
=
is the frequency of the PLLCLK signal.)
PLL
OSCCLK
SYSCLK
f
FLASHCLK
SYSCLK
2 × (SYNR + 1)
2
and f
REFDV + 1
and f
Bus
) must be configured to run between 150 kHz and 200 kHz.
=
Bus
=
f
PLL
2
f
OSCCLK
× OSCCLK
2
from Equation 4 .
f
PLL
can be calculated
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