AN2692 Freescale Semiconductor / Motorola, AN2692 Datasheet - Page 35

• Manufacturer Part Number: AN2692
• Description: MC9S12NE64 Integrated Ethernet Controller
• Manufacturer: Freescale Semiconductor / Motorola

After initialization, the MC9S12NE64 can transmit and receive Ethernet packets on a network. A brief
overview of transmit and receive operations using the MC9S12NE64 is provided in the following sections.
Using the MC9S12NE64 Ethernet Interface
After configured and initialized, the MC9S12NE64 Ethernet interface is easy to use. An overview of
sending and receiving Ethernet packets is described in this section.
Buffer Transmit Operation
To start an Ethernet transmission, the user data, destination address, source address, and length/type
field data must be written to the transmit buffer.
The packet can be transmitted using a START command. The START command is launched by writing
a value of 0x01 to the 2-bit transmit command (TCMD) field in the transmit control and status (TXCTS)
register when the transmitter active status (TXACT) bit is clear. The transmitter automatically appends the
frame check sequence.
Buffer Receive Operation
Valid data is received when the receive buffer (A or B) complete flag is set. The received data is stored
in the receive buffer and is available for user access.
To clear a buffer that has been processed, the receive buffer complete interrupt flag for the corresponding
buffer must be cleared.
If the two receive buffers are full, other incoming Ethernet packets are dropped. The two receive buffers
are full when RXACIF and RXBCIF in the IEVENT register are set to 1.
Freescale Semiconductor
19. Configure EPHY through the EMAC MII management interface — Configure speed, duplex mode,
20. Configure EPHY through the EMAC MII management interface:
21. Start the EPHY clock generators.
22. If auto-negotiation is used, as soon as both auto-negotiation is complete and a link is established,
and flow control EPHY auto-negotiation advertisement by writing to the EPHY auto-negotiate
advertisement register.
a.
b.
–
–
a.
b.
the negotiated pause and duplex settings can be determined from the EPHY MII registers. The
EMAC then must be updated by configuring the RFCE and FDX bits to match the negotiated pause
and duplex settings.
If auto-negotiation is used, start the EPHY clock generators by clearing the DIS100 and DIS10
bit of the EPHYCTL0 register.
If auto-negotiation is not used:
Configure the EPHY interrupts by writing to the EPHY interrupt control register.
Read the EPHY interrupt control register to verify content of the EPHY interrupt control
register.
Configure the EPHY through the EMAC MII management interface and configure speed and
duplex mode by writing to the DPLX and DATARATE bits in the EPHY control register.
Start the EPHY clock generators by clearing the DIS100 and DIS10 bit of the EPHYCTL0
register.
MC9S12NE64 Integrated Ethernet Controller, Rev. 0.2
Using the MC9S12NE64 Ethernet Interface
35