AN2866 Freescale Semiconductor / Motorola, AN2866 Datasheet - Page 19

• Manufacturer Part Number: AN2866
• Description: Migrating from the MC68332 to the ColdFire MCF523x
• Manufacturer: Freescale Semiconductor / Motorola

16 bytes of data. The memories consist of a 512-entry tag array (containing addresses and control bits) and
an 8-Kbyte data array, organized as 2048 x 32 bits.
If the desired address is mapped into the cache memory, the output of the data array is driven onto the
ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped into the
tag memory, a cache miss occurs and the processor core initiates a 16-byte, line-sized fetch. The cache
module includes a 16-byte line fill buffer used as temporary storage during miss processing. For all data
cache configurations, the memory operates in write-through mode, and all operand writes generate an
external bus cycle.
2.4.2.3
The FlexCAN module is a communication controller that implements the CAN 2.0B protocol. The CAN
protocol can be used as an industrial control serial data bus, meeting the specific requirements of real-time
processing, reliable operation in harsh EMI environments, cost-effectiveness, and required bandwidth.
The FlexCAN is based on, and includes, all existing features of the Freescale TouCAN module. The
communication data structure supports both standard data and remote frames (up to 109 bits long) and
extended data and remote frames (up to 127 bits long). Each message’s data block size is programmable
at 0–8 bytes in length, and the bit rate is programmable up to 1 Mbit/sec.
A total of 16 flexible message buffers (MBs), each with 0–8 byte data length, are configurable for received
or transmitted messages, all supporting standard and extended messages. Unused MB space can be used
as general purpose RAM space.
2.4.2.4
The SDRAM controller provides all required signals for glueless interfacing to a variety of
JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software-configurable for
different page sizes. To maintain refresh capability without conflicting with concurrent accesses on the
address and data buses, SRAS, SCAS, DRAMW, SDRAM_CS[1:0], and SCKE are dedicated SDRAM
signals.
The SDRAM controller module provides glueless integration of the SDRAM with the MCF523x. The key
features of the DRAM controller include the following:
2.4.2.5
The Direct Memory Access controller (DMA) module provides an efficient way to move blocks of data
with minimal processor interaction. The DMA module provides four fully programmable channels
(DMA0–DMA3) that allow byte, word, longword, or 16-byte burst line transfers. These transfers are
triggered by software explicitly setting a DCRn[START] bit. In addition to software triggering, the DMA
Freescale Semiconductor
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Support for two independent blocks of SDRAM
Interface to standard SDRAM components
Programmable SRAS, SCAS, and refresh timing
Support for 8-, 16-, and 32-bit wide SDRAM blocks
FlexCAN
SDRAM Controller
Direct Memory Access Controller (DMA)
Migrating from the MC68332 to the ColdFire
®
MCF523x, Rev. 1.0
Device Differences
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