AN2905 Freescale Semiconductor / Motorola, AN2905 Datasheet - Page 2

• Manufacturer Part Number: AN2905
• Description: Clock Mode Selection for MSC8126 Mask Set K98M
• Manufacturer: Freescale Semiconductor / Motorola

Mask Set
1
Each MSC8126 device is labeled with a mask set number (for example mask set 1K98M).
2
Figure 1 shows the functional clock block diagram for mask set K98M. The clock contains an internal system
phase-lock loop (SPLL), bus division factor (BUSDF), clocks for the timers, universal asynchronous
receiver/transmitter (UART), time-division multiplexer (TDM), and direct slave interface (DSI). The SPLL
contains a phase-lock loop feedback division factor (PLLFDF), a PLL input clock division factor (PLLRDF), a
phase frequency detector (PFD) and voltage control oscillator (VCO), and a PLL output clock division factor
(PLLODF). All components in Figure 1 are clock dividers except for the PFD and VCO.
The timers, UART, TDM, and DSI modules are shown as dotted lines in Figure 1 because they can use clocks from
sources other than the 60x-compatible system bus clock. The timer clock sources are selected by the Timer
Configuration Registers, TCFRA and TCFRB. If the system bus clock is the source for the timer, the timer divider
is always two. The timers can also be clocked by the GPIO signals, which are clocked separately from the timer
interface to the IPBus. The UART baud rate is based on the system bus clock/ (16 × SCIBR[12–0]), where the
SCIBR is the SCI Baud-Rate register. The TDM processes the data with the system bus clock. The maximum TDM
data bit rate processing is limited to half of the system bus clock. Each TDM has three clock zones:
2
CLKIN
Mask Set
Clock Configuration
•
•
•
The receiver is clocked by RCLKx.
The transmitter is clocked by TCLKx.
The interface to the local bus is clocked by the system bus clock.
PFD: phase frequency detector
VCO: voltage control oscillator
SPLL: system phase-lock loop
PLLRDF: PLL input clock division factor
PLLFDF: PLL feedback division factor
PLLODF: PLL output clock division factor
BUSDF: system bus division factor
Figure 1. MSC8126 Functional Clock Block Diagram for Mask Set K98M
Division by
PLLFDF
Division by
PLLRDF
Clock Mode Selection for MSC8126 Mask Set K98M, Rev. 0
PFD and
VCO
SPLL
2 X PLLODF
Division by
Timers
UART
TDM
DSI
Division
by
BUSDF
Division
by
BUSDF
Freescale Semiconductor
SC140 Cores
CLKOUT
System Bus