AN2905 Freescale Semiconductor / Motorola, AN2905 Datasheet - Page 3

• Manufacturer Part Number: AN2905
• Description: Clock Mode Selection for MSC8126 Mask Set K98M
• Manufacturer: Freescale Semiconductor / Motorola

The DSI has two clearly separated clock zones:
For details on clocking for the timers, UART, TDM, and DSI, consult the MSC8126 Reference Manual
(MSC8126RM). Table 1 shows the maximum frequencies for the SC140 core and system bus for mask set K98M.
You must ensure that the system design does not exceed these maximum frequencies.
3
All MSC8126 devices use a 5-bit MODCK value to configure the clock mode. Refer to the clock mode chart in
Section 7 for valid settings for mask set K98M. The 5-bit MODCK value is determined at reset by sampling the
following:
The MODCK_H field defines the three most significant bits of the MODCK value. The
the two least significant bits. The following example illustrates how the two sets of values define MODCK. The 5-
bit values are organized for explanation purposes as one 3-bit and one 2-bit number: xxx-yy, where:
Table 2 shows an example of how to derive the MODCK value from the MODCK_H (aka MODCK[3–5]) and
MODCK[1–2]
The example in Table 2 corresponds to a MODCK value of 13: MODCK_H-
mode (MODCK) number is the decimal equivalent of the MODCK value read as a binary value: 01101
clock mode 13. Figure 2 shows an example with clock mode 13 for mask set K98M and the functional clock
diagram assuming a 50 MHz input clock (CLKIN).
Freescale Semiconductor
•
•
Clock Modes
•
•
•
•
SC140 cores frequency
System bus and CLKOUT
DSI clock frequency (HCLKIN)
HRCW[28–30] = 011
HD3/MODCK1 pin is pulled up
HD4/MODCK2 pin is pulled down
The DSI interfaces with the external host asynchronously or via a synchronous interface clocked by
the
The DSI interfaces with the internal local bus via the system bus clock.
Two multiplexed system pins (
MODCK_H field in the Hard Reset Configuration Word (HRCW), corresponding to MODCK[3–5]
xxx =
yy =
values.
HCLKIN
MODCK[1–2]
MODCK_H
signal.
. Three clock mode high bits from the HRCW (bits 28–30) (MODCK[3–5]).
Clock Mode Selection for MSC8126 Mask Set K98M, Rev. 0
. Two clock mode low bits from external inputs.
Table 1. Mask Set K98M Maximum Frequency Limits
Input
Table 2. Clock Mode Example
MODCK[1–2]
300 MHz Device
300 MHz
100 MHz
70 MHz
)
MODCK_H = 011
MODCK1 = 0
MODCK2 = 1
400 MHz Device
MODCK Determination Example
MSC8126
133.3 MHz
400 MHz
70 MHz
MODCK[1–2]
MODCK[1–2]
500 MHz Device
= 011-01. The clock
70 MHz
166.7
500
pins define
Clock Modes
2
= 13
10
=
3