FDC37M60X SMSC Corporation, FDC37M60X Datasheet - Page 134

• Manufacturer Part Number: FDC37M60X
• Description: ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
• Manufacturer: SMSC Corporation

Note 3: This chip uses ISA address bits [A11:A0] to decode the base address of each of its logical
Note:
KYBD (refer to the KYBD controller section of this specification).
Note:
Interrupt
Request Level
Select 0
Default = 0x00
on Vcc POR or
Reset_Drv
LOGICAL
NUMBER
DEVICE
0x07
0x09
NAME
devices.
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero
value AND :
for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
for the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
for the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
for the Serial Port logical device by setting any combination of bits D0-D3 in the IER
and by setting the OUT2 bit in the UART's Modem Control (MCR) Register.
IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Note A.
LOGICAL
Reserved
DEVICE
KYBD
Table 56 - I/O Base Address Configuration Register Description
Table 57 - Interrupt Select Configuration Register Description
0x70 (R/W)
REG INDEX
REGISTER
INDEX
n/a
Bits[3:0] selects which interrupt level is used for
Interrupt 0.
Note: All interrupts are edge high (except ECP/EPP)
0x00= no interrupt selected.
0x01= IRQ1
0x02= IRQ2
0x03= IRQ3
0x04= IRQ4
0x05= IRQ5
0x06= IRQ6
0x07= IRQ7
0x08= IRQ8
0x09= IRQ9
0x0A= IRQ10
0x0B= IRQ11
0x0C= IRQ12
0x0D= IRQ13
0x0E= IRQ14
0x0F= IRQ15
Fixed Base Address: 60,64
Not Relocatable
BASE I/O
134
(NOTE3)
RANGE
DEFINITION
+0 : Data Register
+4 : Command/Status Reg.
BASE OFFSETS
FIXED
STATE
C