FDC37M60X SMSC Corporation, FDC37M60X Datasheet - Page 94

• Manufacturer Part Number: FDC37M60X
• Description: ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
• Manufacturer: SMSC Corporation

BIT 4
ENABLE
The interrupt request enable bit when set to a
high level may be used to
requests from the Parallel Port to the CPU due
to a low to high transition on the nACK input.
Refer to the description of the interrupt under
Operation, Interrupts.
BIT 5 DIRECTION
If mode=000 or mode=010, this bit has no effect
and the direction is always out regardless of the
state of this bit. In all other modes, Direction is
valid and a logic 0 means that the printer port is
in output mode (write); a logic “1” means that
the printer port is in input mode (read).
BITS 6 and 7 during a read are a low level, and
cannot be written.
cFifo (Parallel Port Data FIFO)
ADDRESS OFFSET = 400h
Mode = 010
Bytes written or DMAed from the system to this
FIFO are transmitted by a hardware handshake
to the peripheral using the standard parallel port
protocol.
aligned. This mode is only defined for the
forward direction.
ecpDFifo (ECP Data FIFO)
ADDRESS OFFSET = 400H
Mode = 011
Bytes written or DMAed from the system to this
FIFO, when the direction bit is “0”, are
transmitted by a hardware handshake to the
peripheral using the ECP parallel port protocol.
Transfers to the FIFO are byte aligned.
Data bytes from the peripheral are read under
automatic hardware handshake from ECP into
this FIFO when the direction bit is 1. Reads or
ackIntEn - INTERRUPT REQUEST
Transfers to the FIFO are byte
enable interrupt
94
DMAs from the FIFO will return bytes of ECP
data to the system.
tFifo (Test FIFO Mode)
ADDRESS OFFSET = 400H
Mode = 110
Data bytes may be read, written or DMAed to or
from the system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the
to the parallel port lines using a hardware
protocol handshake.
tFIFO may be displayed on the parallel port data
lines.
The tFIFO will not stall when overwritten or
underrun. If an attempt is made to write data to
a full tFIFO, the new data is not accepted into
the tFIFO. If an attempt is made to read data
from an empty tFIFO, the last data byte is re-
read again.
always keep track of the correct FIFO state. The
tFIFO will transfer data at the maximum ISA
rate so that software may generate performance
metrics.
The FIFO size and interrupt threshold can be
determined by writing bytes to the FIFO and
checking the full and serviceIntr bits.
The writeIntrThreshold can be derermined by
starting with a full tFIFO, setting the direction bit
to “0” and emptying it a byte at a time until
serviceIntr is set. This may generate a spurious
interrupt, but will indicate that the threshold has
been reached.
The readIntrThreshold can be derermined by
setting the direction bit to “1” and filling the
empty tFIFO a byte at a time until serviceIntr is
set. This may generate a spurious interrupt, but
will indicate that the threshold has been
reached.
Data bytes are always read from the head of
tFIFO regardless of the value of the direction bit.
For example if 44h, 33h, 22h is written to the
The full and empty bits must
However, data in the