SSD1325 Solomon Systech, SSD1325 Datasheet - Page 10

• Manufacturer Part Number: SSD1325
• Description: OLED/PLED Driver
• Manufacturer: Solomon Systech

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PIN DESCRIPTION
M, DOF#
These pins are No Connection pins. Nothing should be connected to these pins, nor they are connected
together. These pins should be left open individually.
CL
This pin is the system clock input. When internal clock is enabled, this pin should be left open. Nothing
should be connected to this pin. In this case, the output clock frequency equals to the internal clock
frequency. When internal oscillator is disabled, this pin receives display clock signal from external clock
source.
M/S#
This pin is an input pin and must be pulled high to enable the chip function.
CLS
This pin is internal clock enable. When this pin is pulled high, internal clock is enabled.
The internal clock will be disabled when it is pulled low, an external clock source must be connected to
CL pin for normal operation.
BS0, BS1, BS2
These pins are MCU interface selection input. See the following table:
Table 3 - MCU interface setting
CS#
This pin is the chip select input. The chip is enabled for MCU communication only when CS# is pulled
low.
RES#
This pin is reset signal input. When the pin is low, initialization of the chip is executed.
D/C#
This pin is Data/Command control pin. When the pin is pulled high, the input at D
data. When the pin is pulled low, the input at D
relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams.
R/W# (WR#)
This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin will be used as
Read/Write (R/W#) selection input. Pull this pin to “High” for read mode and pull it to “LOW” for write
mode. When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write operation
is initiated when this pin is pulled low and the CS# is pulled low.
Solomon Systech
BS0
BS1
BS2
6800-parallel
interface
0
0
1
8080-parallel
interface
0
1
1
Serial
interface
0
0
0
7
-D
0
will be transferred to the command register. For detail
Aug 2005
P 10/53 Rev 1.2
7
-D
0
is treated as display
SSD1325