SSD1730 Solomon, SSD1730 Datasheet - Page 9

• Manufacturer Part Number: SSD1730
• Description: SSD1730 MLA Power Chip CMOS
• Manufacturer: Solomon

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Table 8 - Pins for row (common) driver voltage generator
Table 9 - Test circuit pins and Dummy pins
7
SSD1730
Pin Name
C8N
VDD_ROW
AB
XBB
C7N
C1PB
C1NB
-V3B
HC
C5P
C5N
VEM
C6N
VEE
Pin Name
XTST
NC,1 NC2,
NC3, NC4
Rev 2.0
04/2002
Type
I/O
O
O
O
I/O
I/O
I/O
O
I
I/O
I/O
O
I/O
O
Type
I
NC
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Pins for row driver voltage conversion circuit
Pin#
2
3
47
48
4
16
14
13
10
12
9
8
7
6
Pin#
46
11, 25, 26, 34
Pins for VDD_ROW voltage generator
Pins for +V1 voltage generator
Description
The negative-side connection terminal for a
capacitor C11 to generate VDD_ROW output
voltage. (Refer to the application circuit)
This is VDD_ROW output voltage which is the
power supply to the logic circuit part of row driver.
This is the clock output for the external n-channel
MOS transistor control in the +V1 voltage
generator circuit.
This is the clock output for the external p-channel
MOS transistor control in the +V1 voltage
generator circuit.
The negative-side connection terminal for a
capacitor C18 to generate +V1 output voltage.
(Refer to the application circuit)
The positive-side connection terminal for a
capacitor C10 and C11 to generate -V3B output
voltage. (Refer to the application circuit)
The negative-side connection terminal for a
capacitor C10 to generate -V3B output voltage.
(Refer to the application circuit)
This is -V3B output voltage equipped as the middle
voltage level for generating VEE output voltage.
This pin is used to select 5X or 6X step-up mode.
When it is tied to VSS, 5X step-up mode will be
set. When it is tied to -V3B, 6X step-up mode will
be set.
The positive-side connection terminal for a
capacitor C8 and C9 to generate VEM output
voltage. (Refer to the application circuit)
The negative-side connection terminal for a
capacitor C8 to generate VEM output voltage.
(Refer to the application circuit)
This is VEM output voltage equipped as the middle
voltage level for generating VEE output voltage.
The negative-side connection terminal for a
capacitor C9 to generate VEE output voltage.
(Refer to the application circuit)
This is VEE output voltage.
Description
This is a test pin. This pin must be tied to the
VDD_PWR level in normal application.
Dummy Pins. These pins must be left open &
unconnected in normal application.
SOLOMON
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