SSD1858 Solomon Systech, SSD1858 Datasheet - Page 30

• Manufacturer Part Number: SSD1858
• Description: LCD Segment / Common Driver
• Manufacturer: Solomon Systech

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Table 9 - Read Status Byte
Bit Pattern
BUSY ON RES# MF2
MF1 MF0 DS1 DS0
Table 10 - Address Increment Table
RS
0
0
1
1
Table 11 - Commands Required for R/W (WR#) Actions on RAM
R/W (WR) Actions on RAMs
Read/write Data from/to GDDRAM
* No need to resend the command again if it is set previously.
The read / write action to the Display Data RAM does not depend on the display mode. This means the
user can change the RAM content whether the target RAM content is being displayed or not.
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SSD1858
An 8 bits status byte will be placed to the data bus if a read operation is performed if D/C# is low. The
status byte is defined as follow.
To read data from the GDDRAM, input High to R/W(WR#) pin and D/C# pin for 6800-series parallel
mode. Low to E(RD#) pin and High to RS pin for 8080-series parallel mode. No data read is provided
for serial mode. In normal mode, GDDRAM column address pointer will be increased by one
automatically after each data read. Also, a dummy read is required before the first data is read. See
Figure 3 in Functional Description.
To write data to the GDDRAM, input Low to R/W(WR#) pin and High to D/C# pin for 6800-series
parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer
will be increased by one automatically after each data write. The address will be reset to 0 in next data
read/write operation is executed when it is 95.
Remarks: Only read data on Page 0 to Page 7 of the GDDRAM. The data on Icon page (page 8)
cannot be read.
Address Increment is done automatically after data read/write. The column address pointer of
GDDRAM is also affected. It will be reset to 0 in next data read/write operation is executed when it is
95.
7.14 Read Status Byte
7.15 Data Read / Write
R/W (WR) Comment
0
1
0
1
Rev 1.1
09/2002
Command
Read Status
Write Command
Read Status
Write Data
Read Data
Commands Required
Set GDDRAM Page Address
Set GDDRAM Column Address
Read/Write Data
Address Increment
No
No
Yes
Yes
Comment
BUSY=0: Chip is idle
BUSY=1: Chip is executing instruction
ON=0: Display is OFF
ON=1: Display is ON
RES#=0: Chip is idle
RES#=1: Chip is executing reset
MF2-MF0: Manufacturer device ID
DS1,DS0 :
0 0 : 64-row driver
0 1 : 80-row driver
1 0 : 128-row,4 G/S driver
(1011X
(0001X
(0000X
(X
7
X
6
X
5
3
3
3
X
X
X
X
4
2
2
2
X
X
X
X
3
1
1
1
X
X
X
X
2
0
0
0
X
)*
)*
)*
1
X
0
)
SOLOMON