HCTS20D Intersil Corporation, HCTS20D Datasheet

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HCTS20D

Manufacturer Part Number
HCTS20D
Description
Radiation Hardened Dual 4-Input NAND Gate
Manufacturer
Intersil Corporation
Datasheet
September 1995
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• 3 Micron Radiation Hardened SOS CMOS
• Total Dose 200K RAD (Si)
• SEP Effective LET No Upsets: >100 MEV-cm
• Single Event Upset (SEU) Immunity < 2 x 10
• Dose Rate Survivability: >1 x 10
• Dose Rate Upset >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• LSTTL Input Compatibility
• Input Current Levels Ii
Description
The Intersil HCTS20MS is a Radiation Hardened Dual 4-Input
NAND Gate. A low on any input forces the output to a High state.
The HCTS20MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of radia-
tion hardened, high-speed, CMOS/SOS Logic Family.
The HCTS20MS is supplied in a 14 lead Ceramic flatpack
(K suffix) or a SBDIP Package (D suffix).
Ordering Information
HCTS20DMSR
HCTS20KMSR
HCTS20D/
Sample
HCTS20K/
Sample
HCTS20HMSR
(Typ)
- VIL = 0.8V Max
- VIH = VCC/2 Min
NUMBER
PART
TEMPERATURE
-55
-55
o
o
RANGE
C to +125
C to +125
+25
+25
+25
10
o
o
o
C
C
C
RAD (Si)/s 20ns Pulse
5 A at VOL, VOH
|
o
o
C
C
Copyright
Intersil Class
S Equivalent
Intersil Class
S Equivalent
Sample
Sample
Die
SCREENING
12
o
LEVEL
C to +125
©
RAD (Si)/s
Intersil Corporation 1999
o
-9
C
14 Lead SBDIP
14 Lead Ceramic
Flatpack
14 Lead SBDIP
14 Lead Ceramic
Flatpack
Die
2
/mg
Errors/Bit-Day
PACKAGE
420
Pinouts
Functional Diagram
NOTE: L = Logic Level Low, H = Logic level High, X = Don’t Care
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
HCTS20MS
GND
An
Bn
Cn
Dn
NC
A1
B1
C1
D1
Y1
An
H
L
X
X
X
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL
PACKAGE (SBDIP) MIL-STD-183S CDIP2-T14
(FLATPACK) MIL-STD-183S CDFP3-F14
Bn
H
X
X
X
GND
L
NC
INPUTS
A1
B1
C1
D1
Y1
Dual 4-Input NAND Gate
1
2
3
4
5
6
7
TRUTH TABLE
1
2
3
4
5
6
7
Cn
X
X
X
H
L
TOP VIEW
TOP VIEW
Radiation Hardened
Dn
X
X
X
H
L
Spec Number
14
13
12
11
10
9
8
File Number
14
13
12
10
11
9
8
VCC
D2
C2
NC
B2
A2
Y2
OUTPUTS
Yn
H
H
H
H
L
518619
3051.1
VCC
D2
C2
NC
B2
A2
Y2
Yn

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HCTS20D Summary of contents

Page 1

... NUMBER RANGE o o HCTS20DMSR - +125 C Intersil Class S Equivalent o o HCTS20KMSR - +125 C Intersil Class S Equivalent o HCTS20D/ +25 C Sample Sample o HCTS20K/ +25 C Sample Sample o HCTS20HMSR +25 C Die CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | http://www.intersil.com or 407-727-9207 ...

Page 2

Absolute Maximum Ratings Supply Voltage (VCC -0.5V to +7.0V Input Voltage Range, All Inputs . . ...

Page 3

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Input to Output TPHL VCC = 4.5V TPLH VCC = 4.5V NOTES: 1. All voltages referenced to device GND measurements assume RL = 500 , CL = 50pF, Input TR ...

Page 4

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH CONFORMANCE GROUPS Initial Test (Preburn-In) Interim Test I (Postburn-In) Interim Test II (Postburn-In) PDA Interim Test III (Postburn-In) PDA Final Test Group A (Note 1) Group B ...

Page 5

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS OPEN GROUND STATIC BURN-IN I TEST CONNECTIONS (Note 10, 12, 13 STATIC BURN-IN II TEST CONNECTIONS (Note ...

Page 6

Intersil Space Level Product Flow - ‘MS’ Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method ...

Page 7

AC Timing Diagrams VIH INPUT VS VIL TPLH VOH VS OUTPUT VOL TTLH VOH 80% 20% OUTPUT VOL AC VOLTAGE LEVELS PARAMETER HCTS VCC 4.50 VIH 3.00 VS 1.30 VIL 0 GND 0 HCTS20MS AC Load Circuit DUT TPHL CL ...

Page 8

Die Characteristics DIE DIMENSIONS: 2.20 x 2.24(mm) METALLIZATION: Type: SiAl Å Å Metal Thickness: 11k 1k GLASSIVATION: Type: SiO 2 Å Å Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 m ...

Page 9

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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