KSZ8001SLI Micrel Semiconductor, Inc., KSZ8001SLI Datasheet - Page 14

• Manufacturer Part Number: KSZ8001SLI
• Description: 1.8V, 3.3V 10/100BASE-T/TX/F Physical Layer Transceiver
• Manufacturer: Micrel Semiconductor, Inc.

March 2006
Micrel
Receive Clock (RXC): For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes down, and
auto-negotiation is disabled, the receive clock then operates off the master input clock (X1 or TXC). For 10BASE-T links, the receive
clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle. The KSZ8001
synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize the signals at the rising edge of the
clock with 10ns setup and hold times.
Transmit Enable: The MAC must assert TXEN at the same time as the first nibble of the preamble, and de-assert TXEN after the
last bit of the packet.
Receive Data Valid: The KSZ8001 asserts RXDV when it receives a valid packet. Line operating speed and MII mode will
determine timing changes in the following way:
Error Signals: Whenever the KSZ8001 receives an error symbol from the network, it asserts RXER and drives “1110” (4B) on the
RXD pins. When the MAC asserts TXER, the KSZ8001 will drive “H” symbols (a Transmit Error define in the IEEE 802.3 4B/5B
code group) out on the line to force signaling errors.
Carrier Sense (CRS): For 100TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS).
An end-of-stream delimiter, or /T/R symbol pair causes de-assertion of CRS. The PMA layer will also de-assert CRS if IDLE
symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is de-asserted. For 10T
links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an end-of-frame (EOF) marker.
Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, then the KSZ8001
asserts its collision signal, which is asynchronous to any clock.
RMII (Reduced MII) Data Interface
RMII interface specifies a low pin count (Reduced) Media Independent Interface (RMII) intended for use between Ethernet PHYs and
Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
RMII Signal Definition
Signal Name
REF_CLK
CRS_DV
RXD[1:0]
TX_EN
TXD[1:0]
RX_ER
Note:
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•
•
•
•
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For 100BASE-TX link with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last nibble of
the data packet.
For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “ 5D” and remains
asserted until the end of the packet.
It is capable of supporting 10Mb/s and 100Mb/s data rates
A single clock reference is sourced from the MAC to PHY (or from an external source)
It provides independent 2 bit wide (di-bit) transmit and receive data paths
It uses TTL signal levels, compatible with common digital CMOS ASIC processes
Unused MII signals, TXD[3:2], TXER need to be tied to GND when RMII is used
Direction
(with respect to
the PHY)
Input
Output
Output
Input
Input
Output
Direction
(with respect to
the MAC)
Input or Output
Input
Input
Output
Output
Input
(Not Required)
14
Use
Synchronous clock reference for receive, transmit and control
interface
Carrier Sense/Receive Data Valid
Receive Data
Transit Enable
Transit Data
Receive Error
Revision 1.03
KSZ8001