KSZ8001SLI Micrel Semiconductor, Inc., KSZ8001SLI Datasheet - Page 18

• Manufacturer Part Number: KSZ8001SLI
• Description: 1.8V, 3.3V 10/100BASE-T/TX/F Physical Layer Transceiver
• Manufacturer: Micrel Semiconductor, Inc.

March 2006
Micrel
CRS
X
X
TXD7 – 0 Encoding
Inter-frame status bit RXD5 conveys the validity of the upper nibble of the byte of the previous frame. Inter-frame status bit RXD0
indicates whether or not the PHY detected an error somewhere on the previous frame. Both of these bits should be valid in the
segment immediately following a frame, and should stay valid until the first data segment of the next frame begins.
When asserted, inter-frame status bit RXD6 indicates that the PHY has detected a false carrier event.
In order to send receive data to the MAC synchronous to the reference clock, the PHY must pass the data through an elasticity FIFO
to handle any difference between the reference clock rate and the clock at the packet source. The Ethernet specification calls for
packet data to be referenced to a clock with a frequency tolerance of 100ppm (0.01%); however, it is not uncommon to encounter
Ethernet stations with clocks that have frequency errors up to 0.1%. Therefore, the elasticity FIFO should be at least 27 bits * long,
filling to the halfway point before beginning valid data transfer via RX. RX_ER should be asserted if, during the reception of a frame,
this FIFO overflows or underflows.
Only RXD and RX_DV should be passed through the elasticity FIFO. CRS should not be passed through the elasticity FIFO. Instead,
CRS should be asserted for the time the ‘wire’ is busy receiving a frame.
Transmit Path
Transmit data and control information are signaled in ten bit segments, just like the receive path. In 100Mbit mode, each segment
represents anew byte of data. In 10Mbit mode each segment is repeated ten times; therefore, every ten segments represents a new
byte of data. The PHY can sample any one of every 10 segments in 10Mbit mode.
Segment boundaries are delimited by SYNC. The MAC continuously generates a pulse on SYNC every 10 clocks.
Transmit Sequence Diagram
TX- Bit Description
TX_SYNC
TX_CLK
Bits
TX_EN
TX_ER
TXD7-0
TX
RX_DV
0
1
TX_ER
RXD0
RX_ER
from
previous
frame
One Data Byte (Two MII Data Nibble)
TX_EN
Purpose
Transmit Enable – identical to MII
Transmit Error – identical to MII
Encoded Data – see TXD7-0 Encoding Table
RXD1
Speed
0=10Mbit
1=100Mbit
TXD0
TXD1
RXD2
Duplex
0=Half
1=Full
TXD2
18
RXD3
Link
0=Down
1=Up
TXD3
RXD4
Jabber
0=OK
1=Error
TXD4
RXD5
Upper
Nibble
0=invalid
1=valid
TXD5
TXD6
RXD6
False
Carrier
Detected
Revision 1.03
TXD7
RXD7
1
KSZ8001