MCP40D17 Microchip Technology Inc., MCP40D17 Datasheet - Page 35

• Manufacturer Part Number: MCP40D17
• Description: 7-bit Single I 2 C? With Command Code Digital Pot With Volatile Memory In Sc70
• Manufacturer: Microchip Technology Inc.

5.2.5
The Stop bit (see
I
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I
FIGURE 5-6:
Transmit Mode.
5.2.6
“Clock Stretching” is something that the Secondary
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP40D17/18/19 will not strech the clock signal
(SCL) since memory read accesses occur fast enough.
FIGURE 5-7:
FIGURE 5-8:
© 2009 Microchip Technology Inc.
2
C Data Transfer Sequence. The Stop bit is defined as
SDA A / A
SCL
SDA
SCL
SDA
SCL
S
STOP BIT
CLOCK STRETCHING
Figure
1st
Bit Bit
2
Condition
C interface of the other devices.
Stop Condition Receive or
Typical 16-bit I
I
START
2
2nd 3rd 4th 5th 6th 7th 8th
C Data States and Bit Sequence.
5-6) Indicates the end of the
Bit Bit Bit Bit Bit Bit
Data allowed
to change
2
C Waveform Format.
P
Data or
A valid
A/A
1st 2nd 3rd 4th 5th 6th 7th 8th A/A
Bit Bit
5.2.7
If any part of the I
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
5.2.8
The MCP40D17/18/19 expects to receive entire, valid
I
defined as a valid command is due to a bus corruption
and will enter a passive high condition on the SDA
signal. All signals will be ignored until the next valid
START condition and CONTROL BYTE are received.
2
C commands and will assume any command not
Bit Bit Bit Bit Bit
MCP40D17/18/19
ABORTING A TRANSMISSION
IGNORING AN I
AND “FALLING OFF” THE BUS
2
C transmission does not meet the
Condition
STOP
2
Bit
C TRANSMISSION
DS22152B-page 35
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