MCP40D17 Microchip Technology Inc., MCP40D17 Datasheet - Page 37

• Manufacturer Part Number: MCP40D17
• Description: 7-bit Single I 2 C? With Command Code Digital Pot With Volatile Memory In Sc70
• Manufacturer: Microchip Technology Inc.

5.3
At times it may become necessary to perform a
Software Reset Sequence to ensure the MCP40D17/
18/19 device is in a correct and known I
state. This only resets the I
This is useful if the MCP40D17/18/19 device powers up
in an incorrect state (due to excessive bus noise, etc),
or if the Master Device is reset during communication.
Figure 5-11
software reset the device.
FIGURE 5-11:
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP40D17/18/19 is driving an A
on the I
command) and is driving a data bit of ‘0’ onto the I
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP40D17/18/19 holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see a A (the Master Device does not
drive the I
the
MCP40D17/18/19 to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP40D17/18/19, AND then as the Master Device
returns to normal operation and issues a Start condition
while the MCP40D17/18/19 is issuing an A. In this case
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP40D17/18/19 could initiate a write cycle.
© 2009 Microchip Technology Inc.
Start
bit
Note:
S
Note:
MCP40D17/18/19),
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
2
Software Reset Sequence
C bus, or is in output mode (from a Read
2
C bus low to acknowledge the data sent by
This technique should be supported by
any I
I
technique,
AN1028.
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP40D17/18/19.
2
shows the communication sequence to
C Serial EEPROM devices support this
2
Nine bits of ‘1’
C compliant device. The 24XXXX
Software Reset Sequence
which
2
which
C state machine.
Stop bit
Start bit
is
also
documented
2
forces
C Interface
S
P
the
2
in
C
The Stop bit terminates the current I
The MCP40D17/18/19 wait to detect the next Start
condition.
This sequence does not effect any other I
which may be on the bus, as they should disregard this
as an invalid command.
5.4
The MCP40D17/18/19 devices support 2 serial
commands. These commands are:
•
•
The I
support the SMBus version 2.0 Write Byte/Word
Protocol formats and Read Byte/Word Protocol
formats. The SMBus specification defines this
operation is Section 5 of the Version 2.0 document
(August 3, 2000).
This protocol format may be convienient for customers
using library routines for the I
need to do is specify the command (read, write, ...) with
the Device Address, the Register Address, and the
Data.
If higher data throughput is desired, please look at the
MCP4017/18/19 devices which have a simplier I
command format.
Write Operation
Read Operations
2
C command formats have been defined so to
Serial Commands
MCP40D17/18/19
2
C bus, where all they
DS22152B-page 37
2
C bus activity.
2
C devices
2
C