IDT72851L15PF IDT, Integrated Device Technology Inc, IDT72851L15PF Datasheet - Page 12

• Manufacturer Part Number: IDT72851L15PF
• Description: IC FIFO SYNC 4096X18 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72851L15PF

• Function: Synchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 8Kx9x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 80mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72851L15PF

NOTES:
1. m = PAF offset.
2. (256-m) words for the IDT72801; (512-m) words the IDT72811; (1,024-m) words for the IDT72821; (2,048-m) words for the IDT72831; (4,096-m) words for the IDT72841; or (8,192-m)
3. t
4. If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.
NOTES:
1. n = PAE offset.
2. t
3. If a read is performed on this rising edge of the read clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
WCLKA (WCLKB)
WENA2 (WENB2)
(RENB1, RENB2)
WENA2 (WENB2)
(RENB1, RENB2)
RCLKA (RCLKB)
RCLKA (RCLKB)
words for the IDT72851.
rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than t
RENA1, RENA2
rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than t
SKEW2
SKEW2
RENA1, RENA2
(If Applicable)
(If Applicable)
is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between the
is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between the
(WENB1)
(WCLKB)
(WENB1)
WENA1
WCLKA
WENA1
PAEA,
(PAFB)
PAEB
PAFA
n words in FIFO
t
CLKH
t
CLKH
t
SKEW2
t
t
ENS
ENS
t
t
ENS
t
Full - (m+1) words in FIFO
CLKL
ENS
t
CLKL
(1)
Figure 11. Programmable Empty Flag Timing
(2)
Figure 10. Programmable Full Flag Timing
t
t
ENH
ENH
t
t
ENH
ENH
t
PAE
TM
SKEW2
SKEW2
12
(1)
(4)
, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB) rising edge.
, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB) rising edge.
t
PAF
t
ENS
n+1 words in FIFO
t
Full - m words in FIFO
ENS
t
ENH
COMMERCIAL AND INDUSTRIAL
t
SKEW2
t
ENH
(3)
(2)
TEMPERATURE RANGES
(3)
JANUARY 13, 2009
t
PAF
t
PAE
3034 drw 12
3034 drw 11