IDT72851L15PF IDT, Integrated Device Technology Inc, IDT72851L15PF Datasheet - Page 9

• Manufacturer Part Number: IDT72851L15PF
• Description: IC FIFO SYNC 4096X18 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72851L15PF

• Function: Synchronous
• Memory Size: 72K (4K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Quad
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 8Kx9x2
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 80mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72851L15PF

NOTES:
1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second write enable pin. Holding WENA2/LDA (WENB2/LDB) LOW
2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
NOTE:
1. t
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
(RENB1, RENB2)
during reset will make the pin act as a load enable for the programmable flag offset registers.
the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than t
RENA1, RENA2
SKEW1
(WENB2/LDB)
WCLKA (WCLKB)
WENA2 (WENB2)
(RENB1, RENB2)
WENA2/LDA
(EFB, PAEB)
RCLKA (RCLKB)
(FFB, PAFB)
RENA1, RENA2
(QB
is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time between
EFA, PAEA
RSA (RSB)
FFA, PAFA
QA
(If Applicable)
(WENB1)
(DB
WENA1
0
0
DA
(WENB1)
- QB
- QA
WENA1
0
0
- DB
(FFB)
- DA
FFA
8
8
)
(1)
8
8
)
t
SKEW1 (1)
t
CLKH
t
WFF
t
Figure 5. Write Cycle Timing
t
DATA IN VALID
RSF
t
RSF
RSF
Figure 4. Reset Timing
t
RS
t
CLK
t
t
t
RSS
RSS
RSS
TM
9
t
CLKL
SKEW1
t
t
ENS
ENS
, then FFA (FFB) may not change state until the next WCLKA (WCLKB) edge.
t
DS
t
t
t
DH
ENH
ENH
t
WFF
t
t
t
RSR
RSR
RSR
OEA (OEB) = 1
OEA (OEB) = 0
NO OPERATION
NO OPERATION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 13, 2009
(2)
3034 drw 06
3034 drw 05