IDT72V825L15PF IDT, Integrated Device Technology Inc, IDT72V825L15PF Datasheet - Page 2

• Manufacturer Part Number: IDT72V825L15PF
• Description: IC SYNCFIFO 1024X18X2 128-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V825L15PF

• Function: Asynchronous, Synchronous
• Memory Size: 18.4K (1K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V825L15PF

DESCRIPTION (CONTINUED)
First-Out (FIFO) memories with clocked read and write controls. These FIFOs
are applicable for a wide variety of data buffering needs, such as optical disk
controllers, Local Area Networks (LANs), and interprocessor communication.
output port. Each input port is controlled by a free-running clock (WCLK), and
an input enable pin (WEN). Data is read into the synchronous FIFO on every
clock when WEN is asserted. The output port of each FIFO bank is controlled
by another clock pin (RCLK) and another enable pin (REN). The Read Clock
can be tied to the Write Clock for single clock operation or the two clocks can
run asynchronous of one another for dual-clock operation. An Output Enable
pin (OE) is provided on the read port of each FIFO for three-state control of
the output.
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the
programmable flags is controlled by a simple state machine, and is initiated
PIN CONFIGURATIONS
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
Each of the two FIFOs contained in these devices has an 18-bit input and
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
WXOA/HFA
WXOB/HFB
WCLKB
INDEX
WENB
RXOA
RXOB
PAFA
PAEB
PAFB
WXIB
RXIA
RXIB
GND
GND
GND
QA0
QA3
QA5
QA6
QA7
QA1
QA2
QA4
QA8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
V
FFA
V
FLB
FFB
V
CC
CC
CC
1
2
3
4
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15
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25
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31
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34
35
36
37
38
TQFP (PK128-1, ORDER CODE: PF)
TOP VIEW
2
by asserting the Load pin (LD). A Half-Full flag (HF) is available for each FIFO
that is implemented as a single device.
IDT Standard mode and First Word Fall Through (FWFT) mode.
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and
enabling a rising RCLK edge, will shift the word from internal memory to the
data output lines.
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word.
First Word Fall Through (FWFT) mode. The XI and XO pins are used to
expand the FIFOs. In depth expansion configuration, FL is grounded on
the first device and set to HIGH for all other devices in the Daisy Chain.
IDT’s high-speed submicron CMOS technology.
There are two possible timing modes of operation with these devices:
In IDT Standard Mode, the first word written to an empty FIFO will not
In FWFT mode, the first word written to an empty FIFO is clocked directly
These devices are depth expandable using a Daisy-Chain technique or
The IDT72V805/72V815/72V825/72V835/72V845 are fabricated using
102
101
100
99
98
97
96
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COMMERCIAL AND INDUSTRIAL
4295 drw 02
LDA
OEA
RSA
V
GND
EFA
QA17
QA16
GND
QA15
V
QA14
QA13
GND
QA12
QA11
V
QA10
QA9
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
GND
RCLKB
RENB
LDB
OEB
RSB
V
GND
EFB
CC
CC
CC
CC
TEMPERATURE RANGES
FEBRUARY 11, 2009