IDT72V825L15PF IDT, Integrated Device Technology Inc, IDT72V825L15PF Datasheet - Page 21

no-image

IDT72V825L15PF

Manufacturer Part Number
IDT72V825L15PF
Description
IC SYNCFIFO 1024X18X2 128-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V825L15PF

Function
Asynchronous, Synchronous
Memory Size
18.4K (1K x 18)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V825L15PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V825L15PF
Manufacturer:
IDT
Quantity:
1 045
Part Number:
IDT72V825L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V825L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V825L15PFI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V825L15PFI8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Q
D
IDT72V805/72V815/72V825/72V835/72V845
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18
D
NOTES:
1. t
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
WCLK
RCLK
0
0
WCLK
0
edge of RCLK and the rising edge of WCLK is less than t
WEN
RCLK
SKEW1
REN
edge of RCLK and the rising edge of WCLK is less than t
-
- Q
SKEW1
- D
WEN
REN
D
FF
OE
FF
17
17
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus t
LOW
DATA IN OUTPUT REGISTER
t
ENS
NO WRITE
t
SKEW1
1
Figure 25. Write Cycle Timing with Double Register-Buffered FF FF FF FF FF (IDT Standard Mode)
t
(1)
SKEW1
t
CLKH
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
t
ENH
(1)
t
A
1
t
CLK
SKEW1
SKEW1
t
CLKL
, then the FF deassertion time may be delayed an extra WCLK cycle.
. then the FF deassertion may be delayed an extra WCLK cycle.
2
t
WFF
2
t
DS
t
WFF
21
Wd
t
DATA READ
WFF
DATAIN VALID
t
ENS
t
NO WRITE
t
ENS
DS
t
SKEW1
t
DH
t
ENH
(1)
t
ENH
COMMERCIAL AND INDUSTRIAL
t
A
t
WFF
1
TEMPERATURE RANGES
WFF
RFF
NO OPERATION
. If the time between the rising
. If the time between the rising
FEBRUARY 11, 2009
NEXT DATA READ
DATA WRITE
2
t
WFF
4295 drw 25
4295 drw 24
t
DS

Related parts for IDT72V825L15PF