AD8109-EB Analog Devices, AD8109-EB Datasheet - Page 8

• Manufacturer Part Number: AD8109-EB
• Description: 250MHz, 8x8 Buffered Video Crosspoint Switch(Gain=2)
• Manufacturer: Analog Devices

AD8108/AD8109
CE
1
0
0
0
X
PARALLEL DATA
(OUTPUT ENABLE)
(OUTPUT ENABLE)
SER/PAR
(SERIAL)
UPDATE
DATA IN
X
1
1
0
X
UPDATE
A0
A1
A2
CLK
CE
RESET
OUT0 EN
OUT1 EN
OUT2 EN
OUT3 EN
OUT4 EN
OUT5 EN
OUT6 EN
OUT7 EN
D0
D1
D2
D3
CLK
X
f
f
X
X
D1
D0
S
Q
D
CLK
LE
OUT0
Q
B0
DATA IN
X
Data
D0 . . . D3,
A0 . . . A2
X
X
D
Q
D1
D0
S
Q
i
D Q
CLK
LE
OUT0
B1
D
Q
D1
D0
S
Q
DATA OUT
X
Data
NA in Parallel
Mode
X
X
D Q
CLK
LE
OUT0
Table III. Operation Truth Table
B2
D
Q
i-32
D1
D0
S
Q
SWITCH MATRIX
D Q
CLK
CLR
LE
OUT0
EN
D
Q
D1
D0
RESET
X
1
1
1
0
S
64
Q
D Q
CLK
LE
OUT1
B0
D
Q
DECODE
D1
D0
SER/
PAR
X
0
1
X
X
S
Q
D Q
CLK
CLR
LE
OUT6
EN
D
Q
Operation/Comment
No change in logic.
The data on the serial DATA IN line is loaded
into serial register. The first bit clocked into
the serial register appears at DATA OUT 32
clocks later.
The data on the parallel data lines, D0–D3, are
loaded into the 32-bit serial shift register loca-
tion addressed by A0–A2.
Data in the 32-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D1
D0
S
Q
D Q
CLK
LE
OUT7
B0
D
Q
D1
D0
S
Q
D Q
CLK
LE
OUT7
B1
D
Q
OUTPUT ENABLE
D1
D0
S
Q
D Q
CLK
LE
OUT7
8
B2
D
Q
D1
D0
S
Q
D Q
CLK
CLR
OUT7
LE
EN
D
Q
DATA
OUT