AD8330 Analog Devices, AD8330 Datasheet - Page 18

• Manufacturer Part Number: AD8330
• Description: Low Cost DC-150MHz Variable Gain Amplifier
• Manufacturer: Analog Devices

AD8330
Offset Compensation
The AD8330 includes an offset compensation feature, which is
operational in the default condition (no connection to pin OFST).
This loop introduces a high-pass filter function into the signal
path, whose –3 dB corner frequency is at:
where C
and R
maximum uncertainty of about 20%. This evaluates to:
A small amount of peaking at this corner when using small capacitor
values can be avoided by adding a series resistor. Useful combina-
tions are C
R
C
The offset compensation feature can be disabled simply by ground-
ing the OFST pin. This provides a dc-coupled signal path, with
no other effects on the overall ac response. Input offsets must be
externally nulled in this mode of operation, as shown in Figure 15.
Effects of Loading on Gain and AC Response
The differential output impedance R
response of the output stage is optimized for operation with a certain
load capacitance on each output pin, OPHI and OPLO, to
ground, in combination with a load resistance R
these pins. In the absence of these capacitances, there will be a
small amount of peaking at the top extremity of the ac response.
Suitable combinations are: R
C
The gain calibration is specified for an open-circuited load, such
as the high input resistance of an ADC. When resistively loaded,
all gain values are nominally lowered as follows:
Thus when R
the reduction is 9.5 dB; and for R
Gain Errors Due to On-Chip Resistor Tolerances
In all cases where external resistors are used, keep in mind that all
on-chip resistances, including the R
R
be accounted for when calculating the gain with input and output
loading. This sensitivity can be avoided by adjusting the source
and load resistances to bear an inverse relationship as follows:
If R
R
Here the gain is 12 dB lower than the basic value. The reduction
of peak swing at the load can be corrected by using V
which also restores 6 dB of gain; using V
full basic gain while also doubling the peak available output swing.
Output (Input) Common-Mode Control
The output voltages are nominally positioned at the midpoint of
the supply, V
appears at pin CNTR, which is not normally expected to be
loaded (the source resistance is ~4 k ). However, some circum-
stances may require a small change in this voltage, and a resistor
HP
I
S
HP
L
, are subject to variances of up to 20%, which will need to
= R
= 25 pF; R
S
= 10 , f = 10 kHz; C
= 3.3 F, R
G
f
f
= R
INT
HPF
HPF
I
LOADED
HP
/ . The simplest case is when R
is an internal resistance of approximately 480 , having a
is the external capacitance added from OFST to CNTR,
HP
I
then make R
L
S
= 3 nF, R
330
/2, over the range 2.7 V < V
C
2 R
= 150 , the gain is reduced by 6 dB; for R
L
HP
= 75 , C
HP
G
INT
= 0
1
UNLOADED
150
C
C
HP
HP
HP
L
= 180
, f = 100 Hz.
= R
L
HP
in F
= 40 pF; R
L
R
= 0.33 F, R
O
= , C
L
R
/ ; or, if R
L
L
, f = 100 kHz; C
= 50 , it is 12 dB.
O
O
L
and the input resistance,
is 150
S
= 12 pF; R
L
= 1 k and R
S
MAG
= 50 , C
< 6 V, and this voltage
L
HP
= R
= 2 V restores the
= 0 , f = 1 kHz;
and the frequency
L
O
directly across
HP
L
MAG
L
then make
= 150 ,
= 50 pF.
= 33 nF,
L
L
= 150 .
= 1 V,
= 75 ,
(11)
(12)
(13)
–18–
from CNTR to ground can lower this voltage, or one to the supply
will raise it. On the other hand, this pin may be driven by an
external voltage source to set the common-mode level, to satisfy
the needs of a following ADC, for example. Any value from 0.5 V
above ground to 0.5 V below the supply is permissible. Of
course, when using an extreme common-mode level, the avail-
able output swing will be limited, and it is recommended that a
value equal or close to the default of V
may be a few millivolts of offset between the applied voltage and the
actual common-mode level at the output pins.
The input common-mode voltage V
slaved to the output, but with a shifted value:
for V
when V
USING THE AD8330
There are very few precautions that need to be observed in apply-
ing the AD8330 to a wide variety of circumstances. A selection
of specific applications is presented later. Here we discuss a few
general aspects of utilization.
As in all high frequency circuits, careful observation of the ground
nodes associated with each function is important. Three positive
supply pins are provided. VPSI supports the input circuitry, which
may often be operating at a relatively high sensitivity; VPOS,
which supports general bias sources, needs no decoupling; VPSO
is used to bias the output stage, where decoupling may be useful
in maintaining a glitch-free output. Figure 14 shows the general
case, where VPSI and VPSO are each provided with their own
decoupling network, but this may not be needed in all cases.
Because of the differential nature of the signal path, power-supply
decoupling is in general much less critical than in a single-sided
amplifier, and where the minimization of board-level components
is especially crucial, it may be found that these pins need no
decoupling at all. On the other hand, when the signal source is
Figure 14. Power Supply Decoupling and Basic Connections
INPUT,
0V TO 2V MAX
BASIC GAIN BIAS
V
DBS :
V
DBS
CD1
RD1
CMI
0V TO 1.5V
S
= 0.75 and T = 25 C. Thus, the default value for V
= 5 V is 3.01 V (see Figure 12).
NC
0 757
.
VPSI
INHI
INLO
MODE
ENBL
VDBS
V
CNTR
BIAS AND
V-REF
VGA CORE
GAIN INTERFACE
1 12
OFST
.
CMGN
CHPF
V
CM MODE AND
OFFSET CONTROL
CMI
VPOS
CNTR
COMM
OUTPUT
STAGES
at pins INHI, INLO is
OUTPUT
CONTROL
= V
S
/2 be used. There
CNTR
VMAG
NC
V
VPSO
OPHI
OPLO
CMOP
S
GROUND
2.7V–6V
CD2
OUTPUT,
2V MAX
REV. A
CD3
CMI
RD2
(14)