IRCC SMSC Corporation, IRCC Datasheet - Page 38

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

Register Block Four contains the IrDA control
registers.
IrDA
(Address 0)
1.152 Select, bit 7
When the 1.152 Select bit is one, the IrDA
1.152Mbps HDLC-type FIR data rate is selected.
Otherwise the .576Mbps rate is chosen. This bit
only applies to the SCE clock when the Block
Control bits select Mode 2, IrDA HDLC.
CRC Select, bit 6
When the CRC Select bit is one, a hardware-
generated CRC is appended to the frame
payload
transactions (Table 22).
BOF Count High, bits 0 - 3
The BOF Count specifies the number of
additional flags that are used in a BOF
sequence.
the BOF Count number of additional flag
characters ('7E'hex) at the start of every frame,
excluding brick walled frames.
the BOF Count number of additional PA bytes at
the start of every frame, excluding brick walled
frames. The BOF Count is a 12-bit value. This
register, BOF Count High, is the BOF Count
upper nibble.
A2
0
0
0
0
1
1
1
Address
Control
A1
0
0
1
1
0
0
1
data
These registers control the IrDA
For example, at 1.152Mbps, insert
A0
0
1
0
1
0
1
0
during
Register/BOF
Direction
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IrDA
1.152
selec
D7
brick wall count (high nibble)
Table 26 - SCE Register Block Four
t
At 4Mbps insert
FIR
Count
selec
D6
crc
message
t
High
D5
brick wall count (low byte)
38
rx data size (low byte)
tx data size (low byte)
IrDA Control Register
bof count (low byte)
speed, and hardware CRC selection.
registers are read/write.
BOF Count Low (Address 1)
The BOF Count Low register is the lower byte of
the BOF Count.
Brick Wall Count Low (Address 2)
The Brick Wall Count register specifies the
number of additional interframe padding flags
used for brick walled messages. The Brick Wall
Count is a 12-bit value. The Brick Wall Count
Low register is the Brick Wall Count lower byte.
BW Count High/Tx Data Size High
(Address 3)
Brick Wall Count High, bits 4 - 7
The BW Count High register is the upper nibble
of the Brick Wall Count.
Tx Data Size High, bits 0 - 3
The Tx Data Size register specifies the IrLAP-
negotiated maximum number of payload data
bytes per IrDA transmit message frame if
software CRC is selected, or the IrLAP-
negotiated maximum number of payload data
bytes minus the number of CRC bytes if
hardware CRC is selected. This register is used
Description
D4
D3
rx data size (high nibble)
tx data size (high nibble)
(high nibble)
D2
bof count
D1
D0
Default
'C0'hex
'00'hex
'00'hex
'00'hex
'00'hex
'00'hex
'00'hex
The