IRCC SMSC Corporation, IRCC Datasheet - Page 69

• Manufacturer Part Number: IRCC
• Description: INFRARED COMMUNICATIONS CONTROLLER
• Manufacturer: SMSC Corporation

Burst Mode Transmit
Uses FIFO Threshold for Triggered Transmit.
The IrDA 4PPM transmit encoder can deplete
the SCE FIFO faster than an ISA Host can fill it.
The FIFO Threshold can be used to allow the
DMA controller to load enough data into the
FIFO
accommodate system latencies for subsequent
DMA transfer cycles.
otherwise not used for DMA transfers.
DRQ Control
In DMA Burst Mode, DRQ remains active until
the entire DMA data block has been transferred,
as indicated by DMA Terminal Count (TC). The
internal
deactivate DRQ if the DMA block has not been
completely transferred but there is no room left in
the FIFO for more data. As soon as the FIFO
Full becomes inactive, DRQ is reasserted. The
before
FIFO
Full
FIGURE 38 - 32 I/OX CLOCK DMA REFRESH COUNT TIMING
transmission
signal
The FIFO Threshold is
Refresh Interval
Countdown & Reset
DMA Enable
can
DMA Burst
32-Clk Counter
Disable 32-Clk
nDACK
begins
DRQ
temporarily
I/Ox
to
69
Enable 32-Clk
Countdown
32 clocks
internal
temporarily deactivate DRQ (see the 32 I/Ox
Clock DMA Refresh Counter).
Example: Transmit a 256-Byte IrDA Message
1.
2.
3.
max.
Setup and enable the DMA controller for the
256-byte message.
Set
typically this number can be high, e.g. 127,
and set the SCE Modes bits in Register
Block Zero, Address 6 to enable the
transmitter.
The DMA controller proceeds to load the
FIFO
transmitter.
until TC.
FIFO Full or Refresh Interval are active
(Figure 39).
Refresh
the
350ns
until
min.
DRQ is only de-asserted when
appropriate
DMA transfer cycles continue
TxServReq
Interval
signal
FIFO
activates
Threshold,
can
also
the