ADP3211 ON Semiconductor, ADP3211 Datasheet - Page 14

• Manufacturer Part Number: ADP3211
• Description: 7-bit, Programmable, Single-phase, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

a sense element, such as the low−side MOSFET. The
current sense amplifier can be configured several ways,
depending on system optimization objectives, and the
current information can be obtained by:
•
•
•
connected to the output voltage. At the negative input (that
is, the CSFB pin of the CSA), signals from the sensing
element (in the case of inductor DCR sensing, signals from
the switch node side of the output inductors) are connected
with a resistor. The feedback resistor between the
CSCOMP and CSFB pins sets the gain of the current sense
amplifier, and a filter capacitor is placed in parallel with
this resistor. The current information is then given as the
voltage difference between the CSCOMP and CSREF pins.
This signal is used internally as a differential input for the
current limit comparator.
CSCOMP and CSREF pins with the midpoint connected to
the LLINE pin can be used to set the load line required by
the GMCH specification. The current information to set the
load line is then given as the voltage difference between the
LLINE and CSREF pins. This configuration allows the
load line slope to be set independent from the current limit
threshold. If the current limit threshold and load line do not
have to be set independently, the resistor divider between
the CSCOMP and CSREF pins can be omitted and the
CSCOMP pin can be connected directly to LLINE. To
disable voltage positioning entirely (that is, to set no load
line), LLINE should be tied to CSREF.
has a low offset input voltage and the sensing gain is set by
an external resistor ratio.
Active Impedance Control Mode
function of the output current, the signal that is
proportional to the total output current, converted from the
voltage difference between LLINE and CSREF, can be
scaled to be equal to the required droop voltage. This droop
voltage is calculated by multiplying the droop impedance
of the regulator by the output current. This value is used as
the control voltage of the PWM regulator. The droop
voltage is subtracted from the DAC reference output
voltage, and the resulting voltage is used as the voltage
positioning set−point. The arrangement results in an
enhanced feed−forward response.
Voltage Control Mode
voltage mode control loop. The non−inverting input
voltage is set via the 7−bit VID DAC. The VID codes are
At the positive input of the CSA, the CSREF pin is
An additional resistor divider connected between the
To provide the best accuracy for current sensing, the CSA
To control the dynamic output voltage droop as a
A high−gain bandwidth error amplifier is used for the
Output inductor ESR sensing without the use of a
thermistor for the lowest cost
Output inductor ESR sensing with the use of a
thermistor that tracks inductor temperature to improve
accuracy
Discrete resistor sensing for the highest accuracy
http://onsemi.com
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listed in Table NO TAG. The non−inverting input voltage
is offset by the droop voltage as a function of current,
commonly known as active voltage positioning. The output
of the error amplifier is the COMP pin, which sets the
termination voltage of the internal PWM ramps.
sense location using R
controlling the output voltage at the remote sensing point.
The main loop compensation is incorporated in the
feedback network connected between the FB and COMP
pins.
Power−Good Monitoring
voltage via the CSREF pin. The PWRGD pin is an
open−drain output that can be pulled up through an external
resistor to a voltage rail, not necessarily the same V
voltage rail that is running the controller. A logic high level
indicates that the output voltage is within the voltage limits
defined by a range around the VID voltage setting.
PWRGD goes low when the output voltage is outside of this
range.
PWRGD range is defined to be 300 mV less than and
200 mV greater than the actual VID DAC output voltage.
To prevent a false alarm, the power−good circuit is masked
during any VID change and during soft−start. The duration
of the PWRGD mask is set to approximately 130 ms by an
internal timer. In addition, for a VID change from high to
low, there is an additional period of PWRGD masking
before the internal DAC voltage drops within 200 mV of
the new lower VID DAC output voltage, as shown in
Figure 21.
Powerup Sequence and Soft−Start
internally. With GPU pulled to ground, the ADP3211 steps
sequentially through each VID code until it reaches the
boot voltage. With GPU pulled to 5.0 V, the ADP3211 steps
sequentially through each VID code until it reaches the set
VID code voltage. The powerup sequence is illustrated in
Figure 22 for GPU connected to ground and Figure 23 for
GPU connected to 5.0 V.
boot voltage of 1.1 V for IMVP−6.5 CPU applications.
When GPU is connected to ground, the ADP3211A has a
boot voltage of 1.2 V. The boot voltage is the only
difference between the ADP3211 and ADP3211A.
PWRGD MASK
DAC VOLTAGE
At the negative input, the FB pin is tied to the output
The power−good comparator monitors the output
Following the GMCH and CPU specification, the
The power−on ramp−up time of the output voltage is set
When GPU is connected to ground, the ADP3211 has a
VID SIGNAL
INTERNAL
CHANGE
Figure 21. PWRGD Masking for VID Change
100 ms
FB
, a resistor for sensing and
100 ms
CC