ADP3211 ON Semiconductor, ADP3211 Datasheet - Page 26

• Manufacturer Part Number: ADP3211
• Description: 7-bit, Programmable, Single-phase, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

about 120°C; therefore, the R
be less than 13.3 mW at room temperature, or 18.8 mW at
high temperature.
is the input capacitance and feedback capacitance. The
ratio of the feedback to input must be small (less than 10%
is recommended) to prevent accidentally turning on the
synchronous MOSFETs when the switch node goes high.
two main power dissipation components: conduction
losses and switching losses. Switching loss is related to the
time for the main MOSFET to turn on and off and to the
current and voltage that are being switched. Basing the
switching speed on the rise and fall times of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the
switching loss per main MOSFET:
P
where:
n
R
C
lower gate capacitance devices.
following equation:
P
where R
device for a main MOSFET, but such a device usually has
higher on resistance. Therefore, the user must select a
device that meets the total power dissipation (about 0.8 W
to 1.0 W for an 8−lead SOIC) when combining the
switching and conduction losses.
as the main MOSFET (one in total; that is, n
approximately C
8.6 mW (maximum at T
device can be selected as the synchronous MOSFET (two
in total; that is, n
at T
MOSFET at I
each synchronous MOSFET and 446 mW for each main
MOSFET. A third synchronous MOSFET is an option to
further increase the conversion efficiency and reduce
thermal stress.
is best described in terms of the Q
is given by the following equation:
MF
S(MF)
C(MF)
G
ISS
Another important factor for the synchronous MOSFET
The high−side (main) MOSFET must be able to handle
The most effective way to reduce switching loss is to use
The conduction loss of the main MOSFET is given by the
Typically, a user wants the highest speed (low C
For example, an NTMFS4821N device can be selected
Finally, consider the power dissipation in the driver. This
is the total gate resistance.
J
is the total number of main MOSFETs.
is the input capacitance of the main MOSFET.
= 120°C). Solving for the power dissipation per
+ 2
+ D
DS(MF)
O
f
SW
is the on resistance of the MOSFET.
= 15 A and I
SF
ISS
n
= 2), with R
I
MF
O
= 1400 pF (maximum) and R
V
DC
n
2
J
MF
) 1
= 120°C), and an NTMFS4846N
12
I
O
R
DS(SF)
DS(SF)
= 5.0 A yields 178 mW for
R
G
G
n
I
for the MOSFETs and
MF
R
per MOSFET should
= 3.8 mW (maximum
n
2
MF
MF
R
C
DS(MF)
= 1), with
ISS
DS(MF)
(eq. 21)
(eq. 22)
http://onsemi.com
ISS
=
)
26
where Q
MOSFET, and Q
synchronous MOSFET.
(I
Current Limit Set−Point
resistor value for R
ADP3211 is set when the current in R
internal reference current of 20 mA. The current in R
equal to the inductor current times R
using the following equation:
where:
R
the I
R
I
current that will trip current limit.
6.9 kW, which is close to a standard 1% resistance of
6.98 kW.
determined by the following:
(V
is 1.0 V, and the current balancing amplifier gain (A
Using a V
on−resistance at 150°C) results in a per phase limit of 85 A.
Although this number seems high, this current level can
only be reached with a absolute short at the output and the
current limit latchoff function shutting down the regulator
before overheating occurs.
V
than the average per phase current (I
maximum input voltage:
RC Snubber
resistor−capacitor snubber across the low side power
MOSFET. The RC snubber dampens ringing on the switch
P
LIM
CC
LIM
O
I
R
DRV
The previous equation also shows the standby dissipation
To select the current limit set point, we need to find the
In this example, if choosing 20 A for I
The per phase current limit described earlier has its limit
For the ADP3211, the maximum COMP voltage
This limit can be adjusted by changing the ramp voltage
There is also a per phase initial duty−cycle limit at
It is important in any buck topology to use a
PHLIM
COMP(MAX)
. However, users should not set the per phase limit lower
f
is the output load line resistance.
SW
2
LIM
times the V
is the current limit set point. This is the peak inductor
is the current limit resistor. R
+
D
^
LIM
pin to the CSCOMP pin.
GMF
(n
R
V
of 0.55 V, and a R
MF
+ D
COMP(MAX)
) is 3.3 V, the COMP pin bias voltage (V
is the total gate charge for each main
CC
MIN
A
Q
GSF
D
) of the driver.
LIM
GMF
R
LIM
. The current limit threshold for the
R
V
is the total gate charge for each
* V
) n
COMP(MAX)
DS(MAX)
+
R
SF
I
LIM
DS(MAX)
* V
20 mA
V
Q
R
BIAS
R
GSF
* V
LIM
O
O
LIM
of 3.8 mW (low−side
)
. R
) ) I
LIM
BIAS
is connected from
I
/n).
2
LIM
R
CC
is equal to the
LIM
can be found
, R
VCC
(eq. 23)
(eq. 24)
(eq. 25)
(eq. 26)
D
LIM
LIM
) is 5.
BIAS
is
is
)