IDT72V275L15PF IDT, Integrated Device Technology Inc, IDT72V275L15PF Datasheet - Page 22
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
IDT72V275L15PF
Manufacturer Part Number
IDT72V275L15PF
Description
IC FIFO SS 32768X18 15NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V275L15TF8.pdf
(25 pages)
Specifications of IDT72V275L15PF
Function
Synchronous
Memory Size
589K (32K x 18)
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Other names
72V275L15PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V275L15PF
Manufacturer:
TOSHIBA
Quantity:
50
Company:
Part Number:
IDT72V275L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V275L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V275L15PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V275L15PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 32,768 for the IDT72V275 and 65,536 for the IDT72V285.
2. For FWFT mode: D = maximum FIFO depth. D = 32,769 for the IDT72V275 and 65,537 for the IDT72V285.
WCLK
WCLK
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
RCLK
RCLK
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
WEN
WEN
REN
REN
PAE
WCLK and the rising edge of RCLK is less than t
SKEW2
HF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
ENS
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
t
ENH
[
(2)
t
D-1
SKEW2
1
2
,
(3)
D/2 words in FIFO
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
SKEW2
+ 1
(4)
]
, then the PAE deassertion may be delayed one extra RCLK cycle.
words in FIFO
t
t
PAE
CLKH
TM
(1)
2
,
(2)
t
ENS
t
CLKL
22
t
t
ENH
ENS
t
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
[
D-1
D/2 + 1 words in FIFO
t
2
ENH
+ 2
]
(2)
(3)
words in FIFO
,
t
HF
1
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
PAE
). If the time between the rising edge of
t
PAE
[
D-1
2
TEMPERATURE RANGES
D/2 words in FIFO
2
+ 1
]
words in FIFO
n words in FIFO
n+1 words in FIFO
4512 drw 21
4512 drw 20
(1)
,
(2)
(2)
,
(3)