IDT72V275L15PF IDT, Integrated Device Technology Inc, IDT72V275L15PF Datasheet - Page 24

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IDT72V275L15PF

Manufacturer Part Number
IDT72V275L15PF
Description
IC FIFO SS 32768X18 15NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V275L15PF

Function
Synchronous
Memory Size
589K (32K x 18)
Access Time
15ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Other names
72V275L15PF

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FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
where N is the number of FIFOs in the expansion and T
period. Note that extra cycles should be added for the possibility that the t
IDT72V275/72V285 3.3V CMOS SUPERSYNC FIFO
32,768 x 18 and 65,536 x 18
FWFT/SI
WRITE ENABLE
INPUT READY
DATA IN
WRITE CLOCK
For a full expansion configuration, the amount of time it takes for IR of the first
n
(N – 1)*(3*transfer clock) + 2 T
Dn
WEN
IR
WCLK
Figure 20. Block Diagram of 65,536 x 18 and 131,072 x 18 Depth Expansion
FWFT/SI
72V275
72V285
IDT
TRANSFER CLOCK
WCLK
RCLK
REN
OE
TM
OR
Qn
WCLK
is the WCLK
SKEW1
GND
n
24
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
WCLK
IR
Dn
WEN
FWFT/SI
72V275
72V285
IDT
COMMERCIAL AND INDUSTRIAL
RCLK
REN
OR
OE
Qn
TEMPERATURE RANGES
OUTPUT ENABLE
n
OUTPUT READY
READ ENABLE
READ CLOCK
DATA OUT
4512 drw 23

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