SPC8110F0A EPSON Research and Development, Inc., SPC8110F0A Datasheet - Page 11

• Manufacturer Part Number: SPC8110F0A
• Description: LOCAL BUS LCD/CRT VGA CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

PCI Bus
X07-DS-001-21
Key:
Pin Name
AD[31:0]
ADR[31:2]
C/BE[3:0]#
IDSEL
STOP#
FRAME#
IRDY#
PAR
BCLK
TRDY#
DEVSEL#
RST#
PIN DESCRIPTION
CPU INTERFACE
A
I
O
I/O
I/O
I
I
I
O
O
Type
I/O
I
I
I
I/O
I
w/SCH
=
=
=
=
Analog
Input
Output
Bidirectional
Output
Type
4
--
--
--
4
--
--
4
--
4
4
--
30, 43, 50, 62
31
44
47
Pin No.
22-29, 34-41, 51,
55-61,
65-72
20-3, 206-203,
200-193
48
45
49
207
46
202
P
SCH
PD
=
=
=
Power
Schmitt Trigger
Pull Down
Description
PCI multiplexed Address and Data Bus. These lines are driven by the
chip only during read cycles, and are in a hi-Z state at all other times.
Unused VL-Bus Address inputs. These pins should be tied high in PCI
mode.
PCI Bus Command and Byte Enables.
PCI Bus Initialization Device Select.
PCI Bus Stop.
PCI Bus Cycle Frame.
PCI Bus Initiator Ready.
Parity. This line is driven by the chip only during read cycles, and is in a
hi-Z state at all other times. It is always hi-Z and should be tied high in
VL Bus mode.
PCI Bus Clock.
PCI Bus Target Ready.
PCI Bus Device Select.
CPU Reset. The active low reset signal from the CPU clears all internal
registers and forces all signals to their inactive state. On the rising edge of
the RESET# the MDA[0...15] bus is latched in for configuration.
SPC8110F0A
GRAPHICS
11