SPC8110F0A EPSON Research and Development, Inc., SPC8110F0A Datasheet - Page 15

• Manufacturer Part Number: SPC8110F0A
• Description: LOCAL BUS LCD/CRT VGA CONTROLLER
• Manufacturer: EPSON Research and Development, Inc.

X07-DS-001-21
Pin Name
TSTEN
GENIO[3:0]
LOOP1
LOOP2
IOUTX[1:0]
Pin Name
PS1PIN
PS4PIN
Pin Name
SOGVDD
MVDD
BVDD
CVDD
PVDD
AVDD
MCLVDD
SOGVSS
MVSS
BVSS
CVSS
PVSS
MISCELLANEOUS
POWER SAVE MODE CONTROLS
POWER SUPPLY
P
P
P
P
P
P
Type
P
P
P
P
P
P
Type
I w/
PD
I/O w/
PD
I
I
A
Type
I
w/
SCH,
PD
I
w/
SCH,
PD
Pin No.
158, 106, 54, 2
112, 91
32, 64
154
166, 182
135, 141
122, 171
157, 105, 53, 1
111, 124, 104,
90, 81
201, 208, 21,
42, 52, 33, 63
156
181
Output Type
--
2
--
--
--
Output Type
--
--
Pin No.
148
121, 159,
160, 161
143
134
137, 139
Pin No.
150
151
Description
V DD supply for core logic. (3.3V only.)
V DD supply for memory pins. (Either 3.3V or 5.0V.)
V DD supply for bus interface pins. (Either 3.3V or 5.0V.)
V DD supply for control interface pins. (Either 3.3V or 5.0V.)
V DD supply for panel interface pins. (Either 3.3V or 5.0V.)
Analog power supply. (3.3V only.)
VDD supply for MCL logic. (3.3V only.)
VSS supply for core logic.
VSS supply for memory pins.
VSS supply for bus interface pins.
VSS supply for CRT interface pins.
VSS supply for panel interface pins.
Description
Pin used to initiate a power save mode 1. The polarity of this pin is
programmable and has a default polarity of active low. This input has
an internal pull down resistor that has a typical value of 50K/100K
at 5 V/3.3 V respectively. When TSTEN is active, the polarity of
PS1PIN selects the test to be either boundary pin SCAN (PS1PIN = 1)
or pin output drive test (PS1PIN = 0).
Pin used to initiate a power save mode 4. The polarity of this pin is
programmable and has a default polarity of active low. This input has
an internal pull down resistor that has a typical value of 50K/100K
at 5 V/3.3 V respectively.
Description
This pin, when high, sets the SPC8110F0A into either boundary pin
SCAN or pin output drive test, depending on the state of PS1PIN.
This input has an internal pull down resistor that has a typical value of
50K/100K
General purpose I/O pins. Output state of each pin is programmable to
control external devices. See AUX[34h].
Connects to Loop Filter Resister and Capacitor for PLL1, where
suggested values are R=70
Component Values” document, X07G-G-002-xx.
Connects to Loop Filter Resister and Capacitor for PLL2, where
suggested values are R=70
Component Values” document, X07G-G-002-xx.
Balanced current output for the DAC. This pin should be connected to
AGND if the DAC is not required. See “External Reference
Component Values” document, X07G-G-002-xx.
at 5 V/3.3 V respectively.
and C=0.1 uf. See “External Reference
and C=0.1 uf. See “External Reference
SPC8110F0A
GRAPHICS
15