LM3S1110 Luminary Micro, Inc, LM3S1110 Datasheet - Page 12

• Manufacturer Part Number: LM3S1110
• Description: Lm3s1110 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
List of Registers
System Control .............................................................................................................................. 55
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Hibernation Module ..................................................................................................................... 110
Register 1:
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Internal Memory ........................................................................................................................... 130
Register 1:
Register 2:
12
Device Identification 0 (DID0), offset 0x000 ....................................................................... 65
Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 67
LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 68
Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 69
Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 70
Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 71
Reset Cause (RESC), offset 0x05C .................................................................................. 72
Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 73
XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 77
Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 78
Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 80
Device Identification 1 (DID1), offset 0x004 ....................................................................... 81
Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 83
Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 84
Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 86
Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 88
Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 90
Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 91
Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 92
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 93
Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 94
Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 96
Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 98
Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 100
Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 102
Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 104
Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 106
Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 107
Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 109
Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 118
Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 119
Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 120
Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 121
Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 122
Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 124
Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 125
Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 126
Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 127
Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 128
Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 129
Flash Memory Address (FMA), offset 0x000 .................................................................... 135
Flash Memory Data (FMD), offset 0x004 ......................................................................... 136
Preliminary
July 25, 2008