LM3S1110 Luminary Micro, Inc, LM3S1110 Datasheet - Page 8

• Manufacturer Part Number: LM3S1110
• Description: Lm3s1110 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 8-1.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Figure 10-4.
Figure 11-1.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 13-4.
Figure 13-5.
Figure 13-6.
Figure 13-7.
Figure 13-8.
Figure 13-9.
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 303
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 304
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 304
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 15-1.
Figure 15-2.
Figure 18-1.
Figure 18-2.
Figure 18-3.
8
Stellaris
CPU Block Diagram ......................................................................................................... 34
TPIU Block Diagram ........................................................................................................ 35
JTAG Module Block Diagram ............................................................................................ 45
Test Access Port State Machine ....................................................................................... 48
IDCODE Register Format ................................................................................................. 53
BYPASS Register Format ................................................................................................ 54
Boundary Scan Register Format ....................................................................................... 54
External Circuitry to Extend Reset .................................................................................... 56
Power Architecture .......................................................................................................... 58
Main Clock Tree .............................................................................................................. 60
Hibernation Module Block Diagram ................................................................................. 111
Clock Source Using Crystal ............................................................................................ 112
Clock Source Using Dedicated Oscillator ......................................................................... 113
Flash Block Diagram ...................................................................................................... 130
GPIO Port Block Diagram ............................................................................................... 155
GPIODATA Write Example ............................................................................................. 156
GPIODATA Read Example ............................................................................................. 156
GPTM Module Block Diagram ........................................................................................ 196
16-Bit Input Edge Count Mode Example .......................................................................... 200
16-Bit Input Edge Time Mode Example ........................................................................... 201
16-Bit PWM Mode Example ............................................................................................ 202
WDT Module Block Diagram .......................................................................................... 231
UART Module Block Diagram ......................................................................................... 255
UART Character Frame ................................................................................................. 256
IrDA Data Modulation ..................................................................................................... 258
SSI Module Block Diagram ............................................................................................. 295
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 298
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 298
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 299
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 299
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 300
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 301
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 301
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 302
Analog Comparator Module Block Diagram ..................................................................... 332
Structure of Comparator Unit .......................................................................................... 333
Comparator Internal Reference Structure ........................................................................ 334
100-Pin LQFP Package Pin Diagram .............................................................................. 344
108-Ball BGA Package Pin Diagram (Top View) ............................................................... 345
Load Conditions ............................................................................................................ 375
Hibernation Module Timing ............................................................................................. 377
SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 378
®
1000 Series High-Level Block Diagram ............................................................... 27
Preliminary
July 25, 2008