LM3S1162 Luminary Micro, Inc, LM3S1162 Datasheet - Page 35

• Manufacturer Part Number: LM3S1162
• Description: Lm3s1162 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

1.4.4
1.4.4.1
1.4.4.2
1.4.4.3
July 26, 2008
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
Serial Communications Peripherals
The LM3S1162 controller supports both asynchronous and synchronous serial communications
with:
■
■
■
UART (see page 301)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S1162 controller includes three fully programmable 16C550-type UARTs that support data
transfer speeds up to 3.125 Mbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.) In addition, each UART is capable of supporting IrDA.
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
SSI (see page 342)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S1162 controller includes two SSI modules that provide the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
Each SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
Each SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
Each SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
I
The Inter-Integrated Circuit (I
(a serial data line SDA and a serial clock line SCL).
The I
devices, LCDs, tone generators, and so on. The I
diagnostic purposes in product development and manufacture.
2
C (see page 379)
Three fully programmable 16C550-type UARTs
Two SSI modules
One I
2
C bus interfaces to external I
2
C module
2
C) bus provides bi-directional data transfer through a two-wire design
2
C devices such as serial memory (RAMs and ROMs), networking
Preliminary
2
C bus may also be used for system testing and
LM3S1162 Microcontroller
35